Florent Kermarrec
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ea67080462
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litesata: pep8 (E225)
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2015-04-13 15:44:04 +02:00 |
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Florent Kermarrec
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a9b42161c0
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litesata: pep8 (E222)
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2015-04-13 15:29:34 +02:00 |
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Florent Kermarrec
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77cdb953ad
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litesata: pep8 (E401)
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2015-04-13 15:27:36 +02:00 |
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Florent Kermarrec
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8f7751e412
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litesata: pep8 (E203)
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2015-04-13 15:25:40 +02:00 |
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Florent Kermarrec
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d0c5bd377a
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litesata: pep8 (E302)
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2015-04-13 15:12:39 +02:00 |
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Florent Kermarrec
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808e1fe866
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litesata: pep8 (replace tabs with spaces)
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2015-04-13 14:59:00 +02:00 |
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Florent Kermarrec
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ea613cd8ee
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litesata: update build core target generation
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2015-04-09 00:00:25 +02:00 |
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Florent Kermarrec
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60124be293
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adapt LiteSATA to new SoC
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2015-04-01 22:52:19 +02:00 |
Sebastien Bourdeauducq
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6e2a662dd7
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litesata: adapt to new SoC API
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2015-04-01 17:37:53 +08:00 |
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Florent Kermarrec
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9107710f03
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litexxx cores: use default baudrate of 115200 for all tests
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2015-03-20 12:22:53 +01:00 |
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Florent Kermarrec
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236ea0f572
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liteeth: use bios ip_address in example designs
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2015-03-18 18:18:43 +01:00 |
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Florent Kermarrec
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a266deb58e
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LiteXXX cores: fix frequency print in test/test_regs.py
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2015-03-17 16:01:25 +01:00 |
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Florent Kermarrec
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d2cb41bc63
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LiteXXX cores: convert port parameter to int if is digit in test/make.py
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2015-03-17 15:58:21 +01:00 |
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Florent Kermarrec
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d8b59c03a2
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litesata: avoid hack on kc705 platform with new mibuild toolchain management
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2015-03-14 01:08:36 +01:00 |
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Florent Kermarrec
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52f1c45407
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LiteXXX cores: fix test_reg.py
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2015-03-04 23:13:14 +01:00 |
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Sebastien Bourdeauducq
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073641faa1
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litesata: fix permissions and imports
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2015-03-04 00:46:24 +00:00 |
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Florent Kermarrec
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1d4dc45436
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LiteXXX cores: use format in prints
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2015-03-03 10:29:28 +01:00 |
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Florent Kermarrec
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f27e7a4b22
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litesata: remove unneeded clock constraint
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2015-03-03 10:24:05 +01:00 |
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Sebastien Bourdeauducq
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ff29c86fe1
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litesata/kc705: use FMC pin names
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2015-03-03 01:02:50 +00:00 |
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Florent Kermarrec
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649cdeb265
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liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
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2015-03-01 16:48:41 +01:00 |
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Florent Kermarrec
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9e01bf5fdd
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litesata: create example design derived from SoC
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2015-03-01 11:33:38 +01:00 |
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Florent Kermarrec
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c21a7956c8
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liteXXX cores: remove Identifier duplication
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2015-03-01 11:24:58 +01:00 |
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Florent Kermarrec
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67ca0da1d9
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liteXXX cores: share same methodology for on-board tests
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2015-03-01 11:21:12 +01:00 |
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Florent Kermarrec
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7b464b2b1c
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litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
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2015-03-01 11:03:15 +01:00 |
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Florent Kermarrec
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b34be816ec
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liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
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2015-02-28 22:23:48 +01:00 |
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Florent Kermarrec
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0fd1b9df8d
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liteXXX cores: remove redefinition of get_csr_csv
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2015-02-28 21:45:05 +01:00 |
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Florent Kermarrec
|
69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |
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Florent Kermarrec
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8e67d6e69f
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liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
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2015-02-28 11:08:17 +01:00 |
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Florent Kermarrec
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0dfca49e68
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litesata: move file and modify import to misoclib.mem.litesata
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2015-02-28 11:03:24 +01:00 |