Commit Graph

5615 Commits

Author SHA1 Message Date
enjoy-digital 05815c4ecc
Merge pull request #477 from shuffle2/patch-1
diamond: fix include paths
2020-04-27 21:07:27 +02:00
shuffle2 f71014b9fb
diamond: fix include paths
include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
2020-04-27 11:14:18 -07:00
Florent Kermarrec 4dece4ce24 soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). 2020-04-27 19:06:16 +02:00
enjoy-digital c5ef9c7356
Merge pull request #473 from fjullien/memusage
bios: print memory usage
2020-04-27 18:24:43 +02:00
Franck Jullien 3892d7a90a bios: print memory usage
Print memory usage during the compilation of bios.elf.
2020-04-27 16:33:34 +02:00
Florent Kermarrec 9460e048ec tools/litex_sim: use similar analyzer configuration than wiki. 2020-04-27 16:10:41 +02:00
enjoy-digital 443cc72d0a
Merge pull request #476 from enjoy-digital/serv
Add SERV support (The SErial RISC-V CPU)
2020-04-27 13:59:28 +02:00
Florent Kermarrec 1d1a4ecd28 software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning. 2020-04-27 13:47:13 +02:00
Florent Kermarrec fb9e369a19 serv: connect reset. 2020-04-27 13:26:45 +02:00
Florent Kermarrec c4c891dec5 build/icestorm: add verilog_read -defer option to yosys script (changes similar the ones applied to trellis). 2020-04-27 13:17:53 +02:00
enjoy-digital 192849f0b6
Merge pull request #475 from gregdavill/read_verilog_defer
build/trellis: add verilog_read -defer option to yosys script
2020-04-27 13:13:37 +02:00
Greg Davill 642c4b3036 build/trellis: add verilog_read -defer option to yosys script 2020-04-27 20:10:25 +09:30
Florent Kermarrec 71778ad226 serv: update copyrights (Greg Davill found the typos/issues). 2020-04-27 10:27:44 +02:00
Florent Kermarrec 1f9db583fd serv/cores: fix verilog top level (use serv_rf_top instead of serv_top), working :). 2020-04-26 21:05:47 +02:00
Florent Kermarrec 2efd939d06 serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill). 2020-04-26 16:26:57 +02:00
Florent Kermarrec 96e7e6e89a bios/sdram: reduce number of scan loops during cdly scan to speed it up. 2020-04-25 12:51:33 +02:00
Florent Kermarrec 43e1a5d67d targets/kcu105: use cmd_latency=1. 2020-04-25 12:12:27 +02:00
Florent Kermarrec 85a059bf77 bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal.
We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
2020-04-25 12:11:10 +02:00
Florent Kermarrec 038e1bc048 targets/kc705: manual DDRPHY_CMD_DELAY no longer needed. 2020-04-25 11:03:04 +02:00
Florent Kermarrec aaed4b9475 bios/sdram: review/cleanup Command/Clock calibration, set window at the start instead of middle.
Working on KC705 that previously required manual adjustment.
2020-04-25 11:00:21 +02:00
enjoy-digital 33c7b2ce6b
Merge pull request #472 from antmicro/jboc/sdram-calibration
bios/sdram: add automatic cdly calibration during write leveling
2020-04-25 09:59:08 +02:00
enjoy-digital 4608bd1864
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
litex_sim: add option to create SDRAM module from SPD data
2020-04-25 08:27:00 +02:00
Jakub Cebulski a344e20b5e spi_flash: fix building without bitbang 2020-04-24 17:45:17 +02:00
Jędrzej Boczar ab92e81e31 bios/sdram: add automatic cdly calibration during write leveling 2020-04-24 14:00:42 +02:00
Florent Kermarrec 22c3923644 initial SERV integration. 2020-04-23 08:18:41 +02:00
Florent Kermarrec 0b3c4b50fa soc/cores/spi: add optional aligned mode.
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
Florent Kermarrec 6bb22dfe6b cores/spi: simplify. 2020-04-22 12:20:23 +02:00
Florent Kermarrec fc434af949 build/lattice/common: add specific LatticeiCE40SDROutputImpl/LatticeiCE40SDRTristateImpl (thanks @tnt). 2020-04-22 12:01:23 +02:00
Florent Kermarrec 1457c32052 xilinx/common: use a common SDRTristate implementation for Spartan6, 7-Series and Ultrascale. 2020-04-22 10:42:06 +02:00
Florent Kermarrec 69462e6669 build/xilinx/common: add 7-Series/Ultrascale SDROutput/Input. 2020-04-22 10:33:22 +02:00
Florent Kermarrec 65e6ddc6cd lattice/common: add LatticeECP5DDRInput. 2020-04-22 10:13:28 +02:00
Florent Kermarrec 2031f28057 lattice/common: cleanup instances, simplify tritates. 2020-04-22 09:07:38 +02:00
Florent Kermarrec 2d25bcb09c lattice/common: add LatticeiCE40DDRInput, LatticeiCE40SDROutput and LatticeiCE40SDRInput. 2020-04-22 09:07:33 +02:00
Florent Kermarrec 56e1528455 platforms/de0nano: swap serial tx/rx to ease use of cheap FT232 based cables. 2020-04-18 11:38:24 +02:00
Florent Kermarrec 08e4dc02ec tools/remote/etherbone: update import. 2020-04-17 21:30:33 +02:00
Jędrzej Boczar b0f8ee9876 litex_sim: add option to create SDRAM module from SPD data 2020-04-17 14:52:53 +02:00
Florent Kermarrec 19f983c420 targets: manual define of the SDRAM PHY no longer needed. 2020-04-16 11:26:59 +02:00
Florent Kermarrec c0f3710d66 bios/sdram: update/simplify with new exported LiteDRAM parameters. 2020-04-16 10:42:01 +02:00
Florent Kermarrec 3915ed9760 litex_sim: add phytype to PhySettings. 2020-04-16 10:22:43 +02:00
Florent Kermarrec c0c5ae558a build/generic_programmer: move requests import to do it only when needed. 2020-04-16 08:44:36 +02:00
Florent Kermarrec c9ab593989 bios/sdram/ECP5: set ERR_DDRPHY_BITSLIP to 4.
Bitslip software control is now used on ECP5 to move dqs_read.
2020-04-15 19:30:28 +02:00
Florent Kermarrec 2d01882653 setup.py/install_requires: add requests. 2020-04-15 09:27:26 +02:00
Florent Kermarrec 5e149ceda2 build/generic_programmer: add automatic search/download of flash_proxy in repositories if not available locally. 2020-04-15 08:59:03 +02:00
enjoy-digital a298a9e568
Merge pull request #467 from antmicro/region_type_fix
soc_core: Fix region type generation
2020-04-15 07:56:48 +02:00
Mateusz Holenko 77a05b78e8 soc_core: Fix region type generation
Include information about being a linker region.
2020-04-14 21:45:32 +02:00
Florent Kermarrec d44fe18bd9 stream/AsyncFIFO: add default depth (useful when used for CDC). 2020-04-14 17:35:19 +02:00
Florent Kermarrec ded10c89dc build/sim/core/Makefile: add -p to mkdir modules. 2020-04-14 12:38:02 +02:00
enjoy-digital c323e94c83
Merge pull request #464 from mithro/litex-sim-fixes
Improve the litex_sim Makefiles
2020-04-14 12:16:21 +02:00
Florent Kermarrec a8bf02167a litex_setup: raise exception on update if repository has been been initialized. 2020-04-12 19:46:56 +02:00
Tim 'mithro' Ansell 97d0c525ee Remove trailing whitespace. 2020-04-12 10:29:13 -07:00