3196462311
add support for Verilog include paths
2013-12-12 23:17:51 +01:00
adda930c68
fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
2013-12-12 17:37:31 +01:00
adffec35f6
utils/misc: add gcd_multiple function to compute GCD or any number of integers
2013-12-12 17:36:50 +01:00
c13fe1bc63
specials/Memory: allow for more flexibility in memory port signals
2013-12-12 17:36:17 +01:00
135a4fea25
fhdl/verilog: fix representation of negative integers
...
Give the explicit two's complement representation for the given bit width.
This results in less readable code compared to using unary minus,
but fixes a bug when trying to represent the most negative integer.
2013-12-11 22:26:10 +01:00
d6cb981c7a
migen/test/test_signed: add a (currently failing) signed comparison testcase
2013-12-10 23:33:53 +01:00
487df5b174
migen/fhdl/bitcontainer: fix signed arrays (map is an iterator)
2013-12-10 23:32:12 +01:00
fe0263bb9a
mibuild/xilinx_ise: use ngdbuild_opt also for xst case
2013-12-06 12:15:22 +01:00
0aa6329edb
mibuild/xilinx_ise: add support for custom tools and options
2013-12-06 09:16:07 +01:00
e09e85ec8e
usrp_b100 platform
2013-12-03 22:51:52 +01:00
5447eb51ba
add zedboard platform
2013-12-03 22:51:52 +01:00
bfdc14fbc3
add initial ztex_115d platform
2013-12-03 22:51:52 +01:00
8d093a4a08
lx9 fixups
2013-12-03 22:51:52 +01:00
8d3d61ba98
fhdl.size: rename to bitcontainer
2013-12-03 22:51:52 +01:00
86ba9c8bbc
migen.fhdl.size: verify fslice for negative values
2013-12-03 21:39:37 +01:00
c71eb5778f
migen.fhdl.structure: have Cat() flat_iteration-ize its arguments
2013-12-03 21:36:33 +01:00
1bf133755e
migen.fhdl.tools: move flat_iteration to migen.util.misc as tools imports other things
2013-12-03 21:36:33 +01:00
fe67210d77
migen.fhdl.size: add fiter(), fslice(), and freversed()
...
do not overload __len__, __iter__, __reversed__ as not all valid
expressions (ints and bools) have them. furthermore len([]) is and
should be different from flen([]) (the later raises an error). keep
__getitem__ as an exception that proves the rule ;)
2013-12-03 21:36:33 +01:00
ae6b78faeb
genlib/divider: fix diff computation
2013-12-02 17:56:03 +01:00
ad70d056a8
examples/sim/cordic_err: fix rms_err function name
2013-12-02 13:18:37 +01:00
b3c79738e1
examples/cordic/cordic_impl: do not fail if build dir does not exist
2013-12-02 13:03:26 +01:00
dd24fdd356
genlib/sort: add bitonic, combinatorial sorter
...
complete with with api documentation and unittests
2013-12-02 12:56:36 +01:00
ab48316fcd
examples/cordic: scripted exploration of parameters space
2013-12-02 12:56:29 +01:00
9762546c95
genlib/cordic: cleanup, documentation, unittests
2013-12-02 12:56:24 +01:00
e54fa6f5f4
migen/test: if SimCase is a TestCase, it's run in every module that imports it
2013-12-02 12:43:14 +01:00
4eef3b9399
migen/test/support: allow easy re-setUp of the testbench with different parameters
2013-12-02 12:42:59 +01:00
de830dc743
mibuild: use keyword arguments directly in build_cmdline
2013-12-01 17:56:07 +01:00
80be6acfd1
mibuild: add support for Yosys
2013-12-01 17:07:48 +01:00
9b0f43e631
doc/index.rst: drop index and table chapter, index and search are also generated without
2013-11-29 23:47:48 +01:00
cbab9d2bff
setup.py: update repository address
2013-11-29 23:26:52 +01:00
5b26fb10a9
genlib/coding: add docstrings, add it to api doc
2013-11-29 23:25:31 +01:00
5ccd1799f2
genlib/coding, test/test_coding: unittests
2013-11-29 23:25:03 +01:00
205908791a
test/test_fifo: do not use relative import
...
This way the test can simply be run with:
python -m unittest test_fifo.py
2013-11-29 23:18:03 +01:00
502a2871bc
test/test_fifo, genlib/fifo: move test to unittest
2013-11-29 23:11:53 +01:00
cb5e0953aa
migen/test: start unittests
2013-11-29 23:11:23 +01:00
55afab2276
sim: use Simulator as a contextmanager
...
__del__ garbage collector callbacks are too delicate. E.g. imported
modules can be garbage collected before the objects using them. Can't
use os.remove, socket.SHUT_RDWR...
* added a DeprecationWarning if a Simulator is garbage collected without
having its .close() called
* renamed all gc __del__ callbacks to close()
* implemented context manager hooks for Simulator. Use like
with Simulator(TestBench()) as s:
s.run()
2013-11-29 23:05:15 +01:00
cf0fb5350f
doc/api, index: add fhdl.structure, add index/search
...
genindex is needed to generate links between members and search is
useful for the html docs.
2013-11-29 22:40:37 +01:00
be9fea182d
fhdl/structure: clarify usage restrictions of LHS Cat
2013-11-29 22:35:53 +01:00
a836cbb44e
doc/conf.py: no modindex, no numpydoc warnings
...
* do not generate boring modindex for html and latex outputs
* numpydoc_show_class_members=False, to skip undocumented methods
https://github.com/phn/pytpm/issues/3#issuecomment-12133978
2013-11-29 22:31:59 +01:00
73db4944f1
fhdl.structure: document the API
2013-11-29 22:31:55 +01:00
e469e5e539
genlib.fifo: fix docstring section syntax
2013-11-29 22:31:51 +01:00
e1b31ec455
genlib/fifo: clarify we behaviour when writable=0
2013-11-28 22:31:10 +01:00
6e9e0a60eb
setup API documentation, start by documenting fifos
2013-11-28 22:14:20 +01:00
89eb5ee315
add autodoc, numpydoc and doctest to sphinx to generate API doc
2013-11-28 22:14:16 +01:00
6140fd2594
platforms/papilio_pro: add 2x SPI pins
2013-11-25 15:14:58 +01:00
fa741f54fd
specials/Instance: add PreformattedParam
2013-11-25 12:09:51 +01:00
29f7b94e37
bus/wishbone/sram: expose memory component
2013-11-24 23:43:14 +01:00
c5342c5b5c
bus/wishbone: style
2013-11-24 23:42:54 +01:00
6e48682a5e
platforms/papilio_pro: fix clock signal handling
2013-11-24 23:42:31 +01:00
c514fdc4a3
platforms/m1: use definition compatible with Mixxeo for VGA out
2013-11-24 14:00:22 +01:00
Sebastien Bourdeauducq
Robert Jordens