Sebastien Bourdeauducq
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70e97e0456
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Fix various errors from new bitwidth/signedness system conversion
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2012-11-29 23:36:55 +01:00 |
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Sebastien Bourdeauducq
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261166d92b
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fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
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2012-11-29 22:59:54 +01:00 |
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Sebastien Bourdeauducq
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55d143a454
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fhdl/structure: add unary minus
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2012-11-29 22:52:57 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
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Sebastien Bourdeauducq
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fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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59831e0485
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fhdl/structure: improved bits_for function
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2012-11-28 18:39:44 +01:00 |
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Sebastien Bourdeauducq
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11b1e53224
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visit/NodeTransformer: copy most nodes
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2012-11-28 17:50:55 +01:00 |
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Sebastien Bourdeauducq
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a2bcbfdf8f
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fhdl/tools: use NodeTransformer to lower arrays
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2012-11-28 17:46:15 +01:00 |
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Sebastien Bourdeauducq
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3bc15024ac
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fhdl/tools: use NodeVisitor
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2012-11-26 21:40:23 +01:00 |
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Sebastien Bourdeauducq
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1460f069f6
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fhdl/structure: remove deprecated MemoryPort
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2012-11-26 19:36:43 +01:00 |
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Sebastien Bourdeauducq
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27d87c9412
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fhdl/structure: disable we_granularity when larger than width
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2012-11-23 23:08:12 +01:00 |
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Sebastien Bourdeauducq
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f42683b71e
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fhdl/structure/Memory: fix we width
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2012-11-23 19:21:52 +01:00 |
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Sebastien Bourdeauducq
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0f6215a13a
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fhdl/structure: add Memory.get_port API
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2012-11-23 19:17:49 +01:00 |
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Sebastien Bourdeauducq
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9d3e218863
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fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
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2012-11-23 18:38:03 +01:00 |
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Sebastien Bourdeauducq
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3971600917
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fhdl/structure: use sets for memories and instance collections
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2012-11-23 17:20:08 +01:00 |
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Sebastien Bourdeauducq
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51e2e6ecd0
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fhdl/verilog: remove empty cases
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2012-11-18 16:32:51 +01:00 |
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Sebastien Bourdeauducq
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26cf1b8840
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fhdl: make constants hashable
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2012-11-09 20:17:43 +01:00 |
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Sebastien Bourdeauducq
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7744655ef2
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fhdl/visit: add missing self
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2012-11-09 17:37:24 +01:00 |
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Sebastien Bourdeauducq
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13af0ce556
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fhdl: visit module (untested)
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2012-11-09 16:00:11 +01:00 |
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Sebastien Bourdeauducq
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56d4cdeb48
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fhdl/structure: make all values hashable
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2012-11-06 13:51:51 +01:00 |
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Sebastien Bourdeauducq
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8101b68965
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fhdl: fix instance get_io
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2012-09-28 18:02:03 +02:00 |
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Sebastien Bourdeauducq
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c273866b08
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fhdl: support expressions in instance ports
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2012-09-22 20:51:10 +02:00 |
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Sebastien Bourdeauducq
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2fc9cae88a
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fhdl: support inverted clock ports in instances
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2012-09-22 20:50:49 +02:00 |
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Sebastien Bourdeauducq
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2e14569b5c
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fhdl/verilog: sort clock domains by name
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2012-09-11 10:00:03 +02:00 |
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Sebastien Bourdeauducq
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9a18a9df3f
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fhdl: list signals in execution order
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2012-09-11 09:59:37 +02:00 |
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Sebastien Bourdeauducq
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e16353a281
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Multi-clock design support + new instance API
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2012-09-10 23:45:02 +02:00 |
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Sebastien Bourdeauducq
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b45c9546eb
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fhdl/namer: better handling of indices
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2012-09-09 19:33:55 +02:00 |
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Sebastien Bourdeauducq
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589251fffd
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fhdl/tracer: support BUILD_LIST opcode
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2012-09-09 18:53:24 +02:00 |
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Sebastien Bourdeauducq
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910c350021
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fhdl/namer: use execution order indices for variable names as well
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2012-09-09 17:31:35 +02:00 |
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Sebastien Bourdeauducq
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f3e3a3eec7
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fhdl/namer: number objects according to execution order
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2012-09-09 12:27:32 +02:00 |
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Sebastien Bourdeauducq
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51f9a2a963
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fhdl/namer: simplify + more relevant names
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2012-09-09 01:26:33 +02:00 |
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Sebastien Bourdeauducq
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8de192dfbd
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x.bv.width -> len(x)
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2012-07-13 18:32:54 +02:00 |
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Sebastien Bourdeauducq
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9cdc88eadf
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fhdl: len() for Constant
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2012-07-13 18:16:50 +02:00 |
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Sebastien Bourdeauducq
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599ed8d470
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fhdl: fix value_bv for operators
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2012-07-13 17:40:49 +02:00 |
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Sebastien Bourdeauducq
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7f47a2568a
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fhdl: remove _StatementList
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2012-07-13 17:07:56 +02:00 |
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Sebastien Bourdeauducq
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eed8fa374d
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fhdl/arrays: use correct BV for intermediate signals
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2012-07-11 12:06:32 +02:00 |
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Sebastien Bourdeauducq
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ed27783a53
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fhdl: arrays (TODO: use correct BV for intermediate signals)
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2012-07-09 15:16:38 +02:00 |
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Sebastien Bourdeauducq
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398ece8fe2
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fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
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2012-04-30 16:38:40 -05:00 |
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Sebastien Bourdeauducq
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6a52e44d09
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fhdl: support len() on signals
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2012-04-08 18:06:22 +02:00 |
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Sebastien Bourdeauducq
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2a4e49e381
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fhdl: phase out pads
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2012-04-02 19:21:43 +02:00 |
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Sebastien Bourdeauducq
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623e8e436a
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fhdl/verilog: do not attempt to initialize instance and mem output signals
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2012-04-02 12:59:42 +02:00 |
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Sebastien Bourdeauducq
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f3ae22f488
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fhdl/verilog: initialize internal read-only signals with their reset values
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2012-04-01 16:39:11 +02:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
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fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
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Sebastien Bourdeauducq
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bfcd4e636b
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fhdl: handle negative constants correctly
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2012-03-08 20:49:24 +01:00 |
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Sebastien Bourdeauducq
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98e96b3952
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sim: make initialization cycle optional (selectable by function attribute)
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2012-03-06 19:43:59 +01:00 |
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Sebastien Bourdeauducq
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8160ced2e9
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sim: memory access
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2012-03-06 19:29:39 +01:00 |
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Sebastien Bourdeauducq
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db8f8bf2e3
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fhdl: register memory objects with namespace
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2012-03-06 18:33:44 +01:00 |
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Sebastien Bourdeauducq
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90184b22d2
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fhdl/verilog: fix signed constant conversion
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2012-03-06 16:45:44 +01:00 |
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Sebastien Bourdeauducq
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7230508e7c
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fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
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2012-03-06 14:18:22 +01:00 |