Florent Kermarrec
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38d24b637e
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software/bios/sdram: make seed_to_data static
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2015-03-26 23:05:20 +01:00 |
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Florent Kermarrec
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e79a716425
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software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter)
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2015-03-26 22:16:31 +01:00 |
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Florent Kermarrec
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9bc71f374a
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rename sdram mapping to main_ram
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2015-03-21 21:01:46 +01:00 |
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Florent Kermarrec
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b75e4b237d
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software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion of the test zone.
we now need to add another random addressing test to avoid linear access on L2 cache
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2015-03-21 20:29:15 +01:00 |
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Florent Kermarrec
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473997df26
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cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
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2015-03-02 16:52:17 +01:00 |
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Florent Kermarrec
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8280acd3a7
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sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
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2015-03-02 12:17:49 +01:00 |
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Florent Kermarrec
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0980becb56
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sdram: improve memtest by adding 2 different writes/reads
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
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2015-03-02 10:52:22 +01:00 |
Sebastien Bourdeauducq
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36434b62f0
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sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE
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2014-09-03 15:02:38 +08:00 |
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Sebastien Bourdeauducq
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2388bfabc3
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bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705.
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2014-09-03 14:25:26 +08:00 |
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Sebastien Bourdeauducq
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6decb357f1
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bios: add sdrrderr
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2014-09-01 15:23:37 +08:00 |
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Sebastien Bourdeauducq
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57335bdf3f
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bios: add DQ filtering to sdrrd, add sdrrdbuf command
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2014-09-01 14:58:58 +08:00 |
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Sebastien Bourdeauducq
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0ebdf2be6d
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bios/sdram: cleanup
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2014-08-08 21:57:58 +08:00 |
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Sebastien Bourdeauducq
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b61dced909
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bios/sdram: set ODT and RESET_N through DFII
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2014-08-08 21:57:42 +08:00 |
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Florent Kermarrec
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293ac09673
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sdramphy/bios: make sdrrd/sdrwr generic
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2014-08-08 19:25:10 +08:00 |
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Sebastien Bourdeauducq
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dc2024f54d
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bios: remove references to 'DDR' SDRAM, as we also support SDR SDRAM
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2014-05-23 21:31:26 +02:00 |
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Sebastien Bourdeauducq
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1c08aeb21c
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Initial mor1kx (OpenRISC) support
Based on milkymist-ng-mor1kx by Stefan Kristiansson
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2014-05-14 10:24:56 +02:00 |
Sebastien Bourdeauducq
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9e784fc82c
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Generate mem.h from SoC description
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2014-02-21 17:55:05 +01:00 |
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Sebastien Bourdeauducq
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4ba796417d
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software: do not attempt to build network/sdram drivers when cores are not present
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2013-11-24 23:50:09 +01:00 |
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Sebastien Bourdeauducq
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fca0b968e7
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generate linker memory map, move all generated files into the same folder
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2013-11-24 19:50:17 +01:00 |
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Sebastien Bourdeauducq
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26ff6f2a9c
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s6ddrphy: style and other minor fixes
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2013-07-10 20:39:53 +02:00 |
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Florent Kermarrec
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60f1585fef
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use Migen s6ddrphy, generate sdram init_sequence in cif.py
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2013-07-10 19:56:09 +02:00 |
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Sebastien Bourdeauducq
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91d7b656a9
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Switch to LASMI, bug pandemonium
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2013-06-11 14:18:16 +02:00 |
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Sebastien Bourdeauducq
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fdf7f10f54
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Automatically build CSR access functions
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2013-03-25 14:42:48 +01:00 |
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Sebastien Bourdeauducq
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5e6505b946
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bios: print number of memory errors
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2013-02-24 16:51:03 +01:00 |
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Sebastien Bourdeauducq
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dd6eacba62
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Remove uses of the RE signal on field registers
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2012-10-09 19:08:37 +02:00 |
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Sebastien Bourdeauducq
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274a00217e
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bios: asmiprobe command
Because with reordering architectures come order-dependent intermittent bugs.
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2012-08-04 16:32:15 +02:00 |