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6257 Commits

Author SHA1 Message Date
sadullah 19bb1b9b8c update to comply with python-data layout 2020-05-01 23:44:20 -04:00
sadullah 3eb9efd64f BP fpga recent version 2020-05-01 16:27:30 -04:00
sadullah bf864d335b Fix memory transducer bug, --with-sdram for BIOS works, memspeed works 2020-05-01 16:27:27 -04:00
sadullah cf01ea65f3 rebased, minor changes in core.py 2020-05-01 16:25:01 -04:00
sadullah b7b9a1f0fb Linux works, LiteDRAM works (need cleaning, temporary push) 2020-05-01 16:24:58 -04:00
Sadullah Canakci 74140587c8 Create GETTING STARTED 
Rename GETTING STARTED to GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md
 2020-05-01 16:20:35 -04:00
enjoy-digital e853cac6b6
Merge pull request #483 from ilya-epifanov/lattice-openocd-jtag-programmer-erase-flag-and-quiet-output 
Lattice OpenOCD JTAG programmer: removed erase flag and made progress output less noisy
 2020-05-01 21:18:09 +02:00
enjoy-digital a6779b9d61
Merge pull request #491 from gsomlo/gls-spisd-clusters 
software: spisdcard: cosmetic: avoid filling screen with cluster numbers
 2020-05-01 21:17:38 +02:00
Florent Kermarrec b5978b214d .travis.yml: disable python3.5 test (nMigen requires 3.6+). 
As discussed in #479.
 2020-05-01 21:14:17 +02:00
Florent Kermarrec 10371a33f9 CHANGES: update. 2020-05-01 20:13:05 +02:00
Florent Kermarrec bd8a410047 cpu/minerva: add pythondata and use it to compile the sources. 2020-05-01 20:12:02 +02:00
Florent Kermarrec e4a4659d4d litex_setup: add nmigen dependency (used to generate Minerva CPU). 
This also requires Yosys, but Yosys is already expected to be installed separately.
 2020-05-01 19:10:13 +02:00
Florent Kermarrec d3e3ca0618 CHANGES: start listing changes for next release. 2020-05-01 19:07:43 +02:00
Gabriel Somlo c8e3bba4b7 software: spisdcard: cosmetic: avoid filling screen with cluster numbers 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2020-05-01 09:49:16 -04:00
Florent Kermarrec 3c70c83f9b cpu/software: move flush_cpu_icache/flush_cpu_dcache functions to CPUs. 2020-05-01 12:41:14 +02:00
Franck Jullien 74dc444b02 bios: add auto completion for commands 2020-05-01 12:12:35 +02:00
Franck Jullien fc2b8226c5 bios: switch command handler to a modular format 
Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
 2020-05-01 12:12:35 +02:00
Franck Jullien 86cab3d362 bios: move helper functions to their own file 2020-05-01 12:12:35 +02:00
Franck Jullien bc5a1986e2 bios: add terminal history 
Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
 2020-05-01 12:12:07 +02:00
Franck Jullien e764eabda1 builder: add a parameter to pass options to BIOS Makefile 2020-05-01 12:10:50 +02:00
Florent Kermarrec bb70a2325a cpu/software: move CPU specific software from the BIOS to the CPU directories. 
This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.

The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
 2020-05-01 11:04:54 +02:00
Florent Kermarrec 0abc7d4f0b cpu/Minerva: Clone the repository locally for now, we need to create a pythondata repository. 2020-05-01 11:03:07 +02:00
Florent Kermarrec b82b3b7ecf integration/soc: rename usb_cdc to usb_acm. 
As discussed on Discord recently.
 2020-04-30 21:45:53 +02:00
Florent Kermarrec 0a1afbf66f litex/__init__.py: remove retro-compat > 6 months old. 2020-04-30 21:31:58 +02:00
Florent Kermarrec 3531a64173 soc: allow passing custom CPU class to SoC. 
Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
 2020-04-29 20:12:23 +02:00
David Shah 64b505156e Add RDIMM side-B inversion support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-29 12:28:53 +01:00
enjoy-digital 90a6343df1
Merge pull request #488 from enjoy-digital/python3.5 
travis: add back test on python3.5 (python3.6 is recommended but we c…
 2020-04-29 08:48:06 +02:00
Florent Kermarrec 9941e4c16b travis: add back test on python3.5 (python3.6 is recommended but we can try to keep 3.5 compatibility until we have good reason to no longer support it). 2020-04-29 08:43:02 +02:00
Ilya Epifanov 83f4dcb2c6 Added `imac` config for CPUs which implements the most basic working riscv32imac feature set, implemented for VexRiscv 2020-04-28 22:27:35 +02:00
Ilya Epifanov ac1e968351 Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs` 2020-04-28 22:25:57 +02:00
Ilya Epifanov a11f1c39b7 Removed erase flag and made progress output less noisy 2020-04-28 22:22:33 +02:00
enjoy-digital 855d614e5d
Merge pull request #481 from betrusted-io/unfstringify 
propose patch to not break litex for python 3.5
 2020-04-28 19:05:08 +02:00
bunnie 17b766546b propose patch to not break litex for python 3.5 2020-04-29 00:34:19 +08:00
Jakub Cebulski 00f973ea35 spi_flash: extend non-bitbanged flash support 
This commit adds support for memory mapped writes
in the same configuration as memory mapped reads
are currently supported.

It also adds support for accessing registers
and erasing sectors in non-bitbanged single SPI
mode.
 2020-04-28 15:02:55 +02:00
Florent Kermarrec 56aa7897df create first release, add CHANGES and note about Python modules in README. 2020-04-28 11:36:44 +02:00
Florent Kermarrec 6d0896de1d cpu/serv: switch to pythondata package instead of local git clone. 2020-04-28 10:34:39 +02:00
Florent Kermarrec 1b06926882 README: update Python minimal version to 3.6. 2020-04-28 09:02:59 +02:00
Florent Kermarrec ff61b1f6fa litex_setup: disable automatic clone of BlackParrot/Microwatt CPUs, reorder LiteX data. 
The support is not fully finished, so let the user install the pythondata for these CPUs manually with pip.
 2020-04-28 09:01:06 +02:00
enjoy-digital 4d86ab9ded
Merge pull request #399 from mithro/litex-sm2py 
Converting LiteX to use Python modules.
 2020-04-28 08:34:19 +02:00
Florent Kermarrec 5ef869b9eb soc/cpu: add memory_buses to cpus and use them in add_sdram. 
This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
 2020-04-27 23:53:52 +02:00
Florent Kermarrec 467fee3e23 soc/cpu: rename cpu.buses to cpu.periph_buses. 2020-04-27 23:08:15 +02:00
enjoy-digital 317ea7edd1
Merge branch 'master' into litex-sm2py 2020-04-27 22:24:10 +02:00
enjoy-digital 05815c4ecc
Merge pull request #477 from shuffle2/patch-1 
diamond: fix include paths
 2020-04-27 21:07:27 +02:00
shuffle2 f71014b9fb
diamond: fix include paths 
include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
 2020-04-27 11:14:18 -07:00
Florent Kermarrec 4dece4ce24 soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). 2020-04-27 19:06:16 +02:00
enjoy-digital c5ef9c7356
Merge pull request #473 from fjullien/memusage 
bios: print memory usage
 2020-04-27 18:24:43 +02:00
Franck Jullien 3892d7a90a bios: print memory usage 
Print memory usage during the compilation of bios.elf.
 2020-04-27 16:33:34 +02:00
Florent Kermarrec 9460e048ec tools/litex_sim: use similar analyzer configuration than wiki. 2020-04-27 16:10:41 +02:00
enjoy-digital 443cc72d0a
Merge pull request #476 from enjoy-digital/serv 
Add SERV support (The SErial RISC-V CPU)
 2020-04-27 13:59:28 +02:00
Florent Kermarrec 1d1a4ecd28 software/irq: cleanup and make explicit that irqs are not supported with Microwatt and SERV, fix compilation warning. 2020-04-27 13:47:13 +02:00