d0a19c4be8
migen/actorlib/fifo: add FIFO wrapper function
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Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
2015-07-24 13:02:54 +02:00
d73d75007e
misoclib/com/uart: cleanup and add irq condition parameters
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- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
2015-07-24 12:57:42 +02:00
1f1ff5a5e9
migen/fhdl/tools: fix rename_clock_domain when new == old
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Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
2015-07-24 12:48:51 +02:00
b1ea3340f3
litepcie/frontend/dma: add loop counter (useful to detect missed interrupts)
2015-07-22 22:55:11 +02:00
493f424ebd
Merge branch 'master' of https://github.com/m-labs/migen
2015-07-22 21:46:23 +02:00
dfc207aacb
litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow)
2015-07-22 21:44:53 +02:00
5713ae381a
actorlib/packet/Depacketizer: manage layouts without error signal
2015-07-22 21:43:21 +02:00
40740d3ddc
litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
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We should eventually try to use python package_data or data_file for that.
2015-07-22 18:09:04 +02:00
84514cf8d5
uart: remove option to refill HW from uart_write
2015-07-19 23:41:38 +02:00
a501d7c52d
uart: support async phys
2015-07-19 23:37:00 +02:00
097248bce9
uart.c: rx overflow fix and tx simplification
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* fixes the clearing of the rx ringbuffer on rx-overflow
* removes tx_level and tx_cts by restricting the ringbuffer
to at least one slot empty
* agnostic of the details of the tx irq: works for uarts that
generate tx interrupts on !tx-full or on tx-empty.
* only rx_produce and tx_consume need to be volatile
2015-07-19 23:37:00 +02:00
09b33346be
Removed drive strength constraints on VGA/Audio signals
2015-07-14 23:00:26 +02:00
6468fa3db4
xilinx: ensure we chdir() back after build
2015-07-14 12:53:43 -06:00
52bdc29528
mimasv2: style, consistency with other boards
2015-07-14 19:56:00 +02:00
e56d80c7a0
Adding support for Numato Lab Mimas V2 platform
2015-07-14 19:42:51 +02:00
ea8ffd8e80
platforms/kc705: style
2015-07-14 19:42:44 +02:00
35250f5b11
bios: add romboot
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When firmware is small enough, it can be interesting to run code from an embedded blockram memory (faster and not impacted by memory controller activity).
It can also be a fallback option in case boot from flash failed.
To use this, define ROM_BOOT_ADDRESS and initialize the blockram with the firmware data.
2015-07-14 18:01:44 +02:00
6c13879fb6
make.py: use sys.path.insert(0...) to allow external designs to have specific targets derived from a base target
2015-07-13 17:25:50 +02:00
4dca66b23d
misoclib/video/dvisampler: add fifo_depth parameter
2015-07-13 11:03:33 +02:00
e6da1d16b2
wishbone2lasmi: fix "READ_DATA" state
2015-07-09 10:40:32 +02:00
8d6aa82082
mibuild/openocd.py: add support
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Tested with pipistrello and kc705. Needs patches from
https://github.com/jordens/openocd/tree/bscan_spi waiting
to be merged in the openocd queue.
2015-07-07 21:01:31 -06:00
d244eba583
tools/flterm.py: fix kernel-adr support
2015-07-07 14:58:49 +02:00
0545d49294
liteeth/core: add with_icmp parameter
2015-07-06 21:31:20 +02:00
e011f9378f
use sets for leave_out
2015-07-05 22:49:23 +02:00
c100ef6406
liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)
2015-07-05 22:45:53 +02:00
c1ca928ec2
liteeth: small logic optimizations on mac (eases timings on spartan6)
2015-07-05 12:31:52 +02:00
73ea404380
Merge branch 'master' of https://github.com/m-labs/migen
2015-07-05 10:53:32 +02:00
1d1f8510d3
Allow using non-milkymist cables with UrJTAG.
2015-07-05 10:53:09 +02:00
23541b5949
software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)
2015-07-04 21:04:23 +02:00
10eb07526d
bios: show memtest command in help
2015-07-02 17:20:06 +02:00
0df9c16e69
mibuild: Adding error checking around xsvf generation
2015-07-02 16:51:03 +02:00
8daf5e32c1
Adding support for programming with FPGALink
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Steps for getting it set up.
* Get libfpgalink dependencies
sudo apt-get install \
build-essential libreadline-dev libusb-1.0-0-dev python-yaml
* Build libfpgalink
wget -qO- http://tiny.cc/msbil | tar zxf -
cd makestuff; ./scripts/msget.sh makestuff/common
cd libs; ../scripts/msget.sh libfpgalink
cd libfpgalink; make deps
* Convert libfpgalink to python3
wget -O - http://www.swaton.ukfsn.org/bin/2to3.tar.gz | tar zxf -
cd examples/python
cp fpgalink2.py fpgalink3.py
../../2to3/2to3 fpgalink3.py | patch fpgalink3.py
* Set your path's correctly.
export LD_LIBRARY_PATH=$(pwd)/libfpgalink/lin.x64/rel:$LD_LIBRARY_PATH
export PYTHON_PATH=$(pwd)/libfpgalink/examples/python:$PYTHON_PATH
2015-07-02 16:44:39 +02:00
055f7d51fc
mibuild/xilinx: Adding programming with the Digilent Adept tools
2015-07-02 16:03:44 +02:00
7afa3d61d9
mibuild/xilinx: Xilinx's FPGAs do not necessary share the same primitives: add xilinx_s7_special_overrides and specific XilinxDDROutputS7 implementation
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Fix DDROutput implementation on spartan6 (tested with LiteETH's GMII phy)
2015-07-02 09:42:12 +02:00
4509265c70
travis: use use-local for conda install
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http://conda.pydata.org/docs/build_tutorials/pkgs.html
2015-06-30 00:42:56 +02:00
31a447154d
soc: support constants without value
2015-06-28 21:35:37 +02:00
445f0f5d40
Remove self.programmer references in Mercury, as mercury programmer is not implemented.
2015-06-28 18:06:50 +02:00
3ea7ef81a9
Add Mercury dev board to mibuild ( http://www.micro-nova.com/mercury/ )
2015-06-28 16:30:41 +02:00
e913fca8a0
libcompiler-rt: add fixdfdi
2015-06-27 23:51:09 +02:00
a1e3fb16ac
flterm.py: use serial_for_url
2015-06-26 11:40:33 +02:00
04c64eb1d8
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
2015-06-26 00:20:58 +02:00
c615b50735
Merge pull request #14 from olofk/misc_fixes
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Misc fixes
2015-06-25 23:59:42 +02:00
52e6bf6987
litesata/test: Add missing dependency on scrambler in bist_tb
2015-06-26 01:20:25 +02:00
ffb6081720
litesata/example_designs: Add missing clock in phy instantiation
2015-06-26 01:20:25 +02:00
f03c2325d9
Merge pull request #21 from psmears/patch-1
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Minor improvements to wording
2015-06-24 10:46:58 +00:00
125432b5b6
liteeth/example_designs: use new Keep SynthesisDirective
2015-06-23 16:15:28 +02:00
d77a5fc5ac
fhdl/specials: add Keep SynthesisDirective
2015-06-23 16:14:42 +02:00
351e654e9d
software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)
2015-06-23 09:01:34 +02:00
2150e6cfef
pipistrello: run at 83+1/3 MHz, cleanup CRG
2015-06-22 18:56:57 -06:00
01c5051866
liteeth/software: fix wishbone bridge
2015-06-23 01:48:45 +02:00
Florent Kermarrec
Sebastien Bourdeauducq
Robert Jordens
numato
Tim 'mithro' Ansell
Yann Sionneau
William D. Jones
Joe Britton
Olof Kindgren