aec8cd5339
build/xilinx/ise: Fix yosys flow
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The top name changed in 2016 but only XST was changed.
2022-06-28 15:26:14 +02:00
ec9d1c4fd0
CI: Disable more CPUs.
2022-06-27 22:43:01 +02:00
f898423390
test/test_cpu: Diable mor1kx/picorv32 for now due to issue with newer Verilator.
2022-06-27 19:54:50 +02:00
60d0c4ddd4
ci: Compile/Install Verilator from sources (Required for updated Vexriscv-SMP).
2022-06-27 18:53:02 +02:00
4ff839900b
bios/cmd_litedram: Enable sdram_init/mr_write commands also for SDRAM.
2022-06-27 17:49:39 +02:00
c4e3962def
soc/add_etherbone: Expose IP Broadcast capability.
2022-06-27 15:46:57 +02:00
6541a6c93b
build: gowin lattice/diamond lattice/oxide lattice/radiant microsemi quicklogic move to GenericToolchain
2022-06-26 21:40:56 +02:00
1f9bf1bd06
build/generic_toolchain: build_dir, vns now members. Adds build_placement_constraints call. Write verilog ASAP
2022-06-26 21:39:29 +02:00
564c062074
build/xilinx/vivado: use GenericToolchain
2022-06-26 09:06:20 +02:00
8446c5b342
build/anlogic: use GenericToolchain
2022-06-26 09:05:58 +02:00
b75a6ba636
build/lattice/icestorm: move parse_device and pnr_opts to finalize method
2022-06-26 09:05:22 +02:00
418d0f3c0d
build/generic_toolchain: finalize() method: for toolchain specifics tasks one platform ready
2022-06-26 09:04:00 +02:00
83f3c42b89
build/sim/verilator: add (unused) backend parameter
2022-06-25 18:15:48 +02:00
4a3c19cedc
build/lattice/icestorm: add edalize as alternate backend
2022-06-25 17:10:23 +02:00
04617027f4
build/lattice/icestorm: refactor the build options string for yosys and NextPnr
2022-06-25 15:36:38 +02:00
c8b336957f
build/generic_toolchain, soc/integration/builder: introducing a backend argument and edalize as alternate backend
2022-06-25 15:22:30 +02:00
d1e610c400
build/{generic_toolchain, lattice/icestorm, lattice/trellis}: remove toolchain dependants parameters for build_io_constraints, build_timing_constraints, build_placement_constraints. Those must be intercepted at the level of the specific toolchain.
2022-06-24 21:11:31 +02:00
7117de0f1f
build/lattice/icestorm/trellis: Generate Yosys script in build_project.
2022-06-24 10:33:51 +02:00
4c978bf463
build/generic_toolchain: Add add_false_path_constraint and remove it from altera/quartus, lattice/trellis.
2022-06-24 10:24:01 +02:00
6b59eb5cfe
build/generic_toolchain/add_period_constraint: Integrated rounding to lowest picosecond and remove add_period_constraint from altera/quartus.
2022-06-24 10:19:59 +02:00
08a3b0ae4a
build/generic_toolchain: Add build_placement_constraints method and switch other methods to *args, **kwargs for now.
2022-06-24 10:17:02 +02:00
1ecb9cec0a
build/generic_toolchain: Rename constraints methods to build_io_constraints/build_timing_constraints.
2022-06-24 10:12:36 +02:00
08cc384a0c
build/generic_toolchain: Fix build/copyrights and do minor cosmetic changes.
2022-06-24 09:51:46 +02:00
9db1d9e49f
toolchain: implement generic toolchain and devices toolchain refactoring
2022-06-24 09:20:42 +02:00
fa234e8ed8
Do not call spisdcard_select for CMD0.
2022-06-23 16:17:05 +02:00
e4c81e8fdf
Merge pull request #1338 from p-woj/litesdcard-init
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software/liblitesdcard: Fix condition in sdcard_init
2022-06-22 19:42:23 +02:00
ee1af96ab7
CHANGES: Update.
2022-06-22 18:13:49 +02:00
e141826fd8
software/liblitesdcard: Fix condition in sdcard_init
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Instead of retrying `sdcard_app_send_op_cond` until it returns an error,
retry until it completes successfully and the command response has the
busy bit set.
2022-06-22 14:44:28 +02:00
1a90549fa3
interconnect/axi/axi_full: Switch to our own AXI Interconnect (Shared & Crossbar).
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We were not able to simulate verilog_axi interconnect/crossbar correctly since to what
seems to be a simulation mismatch. The code also seems to requires fixing some synthesis
issues with Yosys. When tested with Vivado, the SoC was also miss-behaving (not booting
correctly).
The simulation mismatch issue is logged here: https://github.com/enjoy-digital/litex_verilog_axi_test/issues/1
Since we already had our own AXI-Lite interconnect, creating our AXI interconnect can be
largely based on it with only minor modifications, so switch to it. This also allow simplification
in the interconnect selection/instance.
2022-06-20 19:51:31 +02:00
573479b395
interconnect:axi/axi_lite/interconnect: Cosmetic cleanups.
2022-06-20 19:13:44 +02:00
bb1702e6d5
integration/export: Align MEM_REGIONS for BIOS display with mem_list.
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Before:
litex> mem_list
Available memory regions:
ROM 0x00000000 0x10000
SRAM 0x01000000 0x2000
AXI_RAM 0x00010000 0x1000
AXI_DP_RAM_A 0x00011000 0x1000
AXI_DP_RAM_B 0x00012000 0x1000
AXI_RAM_REG 0x00013000 0x1000
AXI_RAM_FIFO 0x00014000 0x1000
AXI_RAM_XBAR 0x00100000 0x10000
AXI_RAM_INT 0x00200000 0x10000
CSR 0x82000000 0x10000
After:
litex> mem_list
Available memory regions:
ROM 0x00000000 0x10000
SRAM 0x10000000 0x2000
AXI_RAM 0x00010000 0x1000
AXI_DP_RAM_A 0x00011000 0x1000
AXI_DP_RAM_B 0x00012000 0x1000
AXI_RAM_REG 0x00013000 0x1000
AXI_RAM_FIFO 0x00014000 0x1000
AXI_RAM_XBAR 0x00100000 0x10000
AXI_RAM_INT 0x00200000 0x10000
CSR 0xf0000000 0x10000
2022-06-20 15:21:16 +02:00
b00d22f56a
Merge pull request #1334 from antmicro/move_to_f4pga
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Move from deprecated Symbiflow to F4PGA
2022-06-20 11:56:42 +02:00
b8ee713dba
Merge pull request #1331 from cr1901/gowin-win
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Gowin: Fix `copyfile` paths
2022-06-20 11:32:47 +02:00
b66bd171cc
litex_setup: Use recursive clone for litex_verilog_axi.
2022-06-20 11:23:00 +02:00
32d1589fb8
litex_setup: Move valentyusb to Misc Cores and also install litex_verilog_axi.
2022-06-20 11:01:47 +02:00
9b6c9e6630
litex_setup: Switch to specific branch when initializing repositories.
2022-06-20 10:43:30 +02:00
ef2f1bd65b
Merge pull request #1333 from gsomlo/gls-noboot-warning
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bios/main: Wrap CONFIG_NO_BOOT around boot_sequence()
2022-06-20 08:37:03 +02:00
b86629a615
Merge pull request #1335 from benstobbs/valentyusb-proper-install
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Move valentyusb install to litex_setup.py
2022-06-20 08:36:44 +02:00
ca97d91424
clone correct valentyusb branch
2022-06-19 12:58:01 +01:00
db3fa1efc7
move valentyusb install to litex_setup.py
2022-06-19 12:51:14 +01:00
cbd873a33e
test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
839ca545a4
build: quicklogic: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
2c0f59536c
build: xilinx: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
0941459061
integration/soc: Add initial AXI-full support.
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Main bus can now be switched to AXI-full with --bus-standard=axi.
The interconnect will be AXI-Full (Using Alex Forenchich's verilog_axi
Interconnect and Crossbar) but ROM/SRAM will still be in AXI-Lite (Will
be switched to AXI-full in the future).
This gives a first working version that can be used for further improvements.
Note that the interconnect can also be selected by --bus-interconnect=shared or
crossbar.
2022-06-17 16:21:31 +02:00
8394e93742
interconnect/axi/axi_full: Add AXI Interconnect (Shared and Crossbar).
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For now reusing Alex Forenchich's modules wrapped with LiteX.
2022-06-17 16:07:05 +02:00
bc667c6456
interconnect/axi/axi_full/AXIInterface: Add name/bursting parameters.
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To add compatibility with AXILiteInterface and allow dynamic selection.
2022-06-17 16:04:25 +02:00
333aadbf6e
integration/soc/SoC: Switch to finalize and finalize submodule only at the end.
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This avoid elaborating submodules before adding the final modules and gives more
flexibility.
2022-06-17 16:01:28 +02:00
4c0a943996
interconnect/axi: Create axi directory and split code by type/functionnality.
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AXI code is now too large to be contained in a single file, splitting code by type/functionnality
will simplify future additions.
2022-06-16 18:53:12 +02:00
c4e07e2a5b
integration/soc: Allow Bus Interconnect to use either InterconnectShared or Crossbar and add --bus-interconnect command line parameter.
2022-06-16 17:47:13 +02:00
6942e3240c
interconnect/axi/AXIDownConverter: Switch to AXI-Full (Inspired from AXIUpConverter).
2022-06-16 16:16:49 +02:00
Christian Klarhorst
enjoy-digital
Gwenhael Goavec-Merou
Rouven Broszeit
Piotr Wojnarowski
Ben Stobbs
Robert Szczepanski