Florent Kermarrec
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93de581931
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soc: add shadow_address parameter
When don't necessary want to have shadow memories and be able to start CSR at address 0x00000000(for example with an X86 CPU)
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2015-04-17 13:42:29 +02:00 |
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Florent Kermarrec
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fc68d915c1
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global: pep8 (E261, E271)
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2015-04-13 17:16:12 +02:00 |
|
Florent Kermarrec
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f68423f423
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global: pep8 (E302)
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2015-04-13 16:47:22 +02:00 |
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Florent Kermarrec
|
d9e09707ae
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global: pep8 (replace tabs with spaces)
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2015-04-13 16:19:55 +02:00 |
Sebastien Bourdeauducq
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3a2b677f85
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soc,cpuif: support user defined constants
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2015-04-09 00:34:36 +08:00 |
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Florent Kermarrec
|
c9c11e7aa8
|
soc: add memory.name_override to name when adding csrbankarray.srams to csr_regions
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2015-04-03 12:45:32 +02:00 |
|
Sebastien Bourdeauducq
|
85b3cced22
|
use str.format
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2015-04-03 17:43:46 +08:00 |
|
Sebastien Bourdeauducq
|
2900429e65
|
soc: use set
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2015-04-02 00:14:56 +08:00 |
|
Sebastien Bourdeauducq
|
369086a178
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soc: simplify integrated memory parameters
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2015-04-02 00:09:38 +08:00 |
|
Sebastien Bourdeauducq
|
9599eb6fae
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soc: remove cpu_boot_file argument
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2015-04-01 17:32:45 +08:00 |
|
Sebastien Bourdeauducq
|
fb86445d14
|
soc: remove cpu_or_bridge and with_cpu arguments
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2015-04-01 17:29:51 +08:00 |
|
Sebastien Bourdeauducq
|
a148af97ba
|
soc: retrieve csr and memory regions using methods
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2015-04-01 16:49:32 +08:00 |
|
Sebastien Bourdeauducq
|
8b19a11cd7
|
soc: use add_wb_master function
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2015-04-01 15:56:54 +08:00 |
|
Sebastien Bourdeauducq
|
2a1112b912
|
soc: simplify/fix csr busword
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2015-04-01 15:48:56 +08:00 |
|
Sebastien Bourdeauducq
|
04f29e97e2
|
soc: remove unnecessary imports
|
2015-04-01 15:15:09 +08:00 |
|
Sebastien Bourdeauducq
|
5113301130
|
soc: improve memory region conflict check
|
2015-04-01 15:14:02 +08:00 |
|
Sebastien Bourdeauducq
|
980791e2b8
|
soc: remove ns function
|
2015-04-01 14:33:12 +08:00 |
|
Florent Kermarrec
|
9bc71f374a
|
rename sdram mapping to main_ram
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2015-03-21 21:01:46 +01:00 |
|
Florent Kermarrec
|
c55199deb9
|
misoclib/soc: add _integrated_ to cpu options to avoid confusion
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2015-03-21 20:51:37 +01:00 |
|
Florent Kermarrec
|
28d04ec300
|
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
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2015-03-14 00:49:19 +01:00 |
|
Florent Kermarrec
|
1b58813d13
|
soc: do_exit is now provided by modules
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2015-03-09 17:18:42 +01:00 |
|
Florent Kermarrec
|
af66ca7bad
|
uart: add phy autodetect function
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2015-03-06 10:19:29 +01:00 |
|
Florent Kermarrec
|
bee8ccf6c7
|
soc: enforce cpu_reset_address to 0 when with_rom is True
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2015-03-06 08:21:16 +01:00 |
|
Florent Kermarrec
|
0bcd6daf63
|
soc: remove is_sim function
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2015-03-03 10:15:11 +01:00 |
|
Florent Kermarrec
|
f58394f6af
|
soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
|
Florent Kermarrec
|
bd4d3cd73b
|
uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
|
Florent Kermarrec
|
144ee7ea9f
|
soc: fix register_rom
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2015-02-28 23:51:51 +01:00 |
|
Florent Kermarrec
|
5c43d4d091
|
litescope: create example design derived from SoC that can be used on all targets
|
2015-02-28 22:19:24 +01:00 |
|
Florent Kermarrec
|
165a5b6760
|
soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
|
2015-02-28 20:04:51 +01:00 |
|
Florent Kermarrec
|
8564b7eb6a
|
soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
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2015-02-28 11:44:14 +01:00 |
|
Florent Kermarrec
|
69e869893d
|
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |