Florent Kermarrec
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408d0fd2dd
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liteeth: use default programmer in make.py
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2015-03-17 12:12:21 +01:00 |
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Florent Kermarrec
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ec6ae75065
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liteeth: use CRG from Migen in base example
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2015-03-17 12:11:51 +01:00 |
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Florent Kermarrec
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a874f85854
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litescope: use CRG from Migen
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2015-03-17 11:52:54 +01:00 |
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Florent Kermarrec
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faf185d58d
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liteeth: make gmii phy generic
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2015-03-16 23:04:37 +01:00 |
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Florent Kermarrec
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d8b59c03a2
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litesata: avoid hack on kc705 platform with new mibuild toolchain management
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2015-03-14 01:08:36 +01:00 |
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Florent Kermarrec
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28d04ec300
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soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
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2015-03-14 00:49:19 +01:00 |
Sebastien Bourdeauducq
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32676fffd2
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soc/sdram: sync with new mibuild toolchain management
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2015-03-13 23:19:08 +01:00 |
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Florent Kermarrec
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c3c7f627d9
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liteeth/phy: typo (thanks sb)
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2015-03-12 21:54:10 +01:00 |
|
Florent Kermarrec
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cd6c04b24f
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soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx
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2015-03-12 17:12:56 +01:00 |
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Florent Kermarrec
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767d45727a
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uart/liteeth: only import the phy we are going to use (UARTPHYSim cannot be imported on Windows since based on pty).
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2015-03-12 16:57:38 +01:00 |
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Florent Kermarrec
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b157031e8a
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uart/sim: add pty (optional, to use flterm)
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2015-03-09 23:29:06 +01:00 |
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Florent Kermarrec
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6cbf13036b
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liteeth/mac: fix padding limit (+1), netboot OK with sim platform
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2015-03-09 20:59:34 +01:00 |
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Florent Kermarrec
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47cceea222
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liteeth/mac: use Counter in sram and move some logic outside of fsms
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2015-03-09 20:22:14 +01:00 |
|
Florent Kermarrec
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b10836a8eb
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liteeth/phy/sim: create ethernet tap in __init__ and destroy it in do_exit
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2015-03-09 17:21:29 +01:00 |
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Florent Kermarrec
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1b58813d13
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soc: do_exit is now provided by modules
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2015-03-09 17:18:42 +01:00 |
|
Florent Kermarrec
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360c849f21
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liteeth: fix cnt_inc in IDLE state (we should wait sop to inc counter)
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2015-03-09 13:23:39 +01:00 |
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Florent Kermarrec
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5dbd8af4be
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liteeth: do not insert CRC/Preamble in simulation to allow direct connection to ethernet tap
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2015-03-09 13:23:37 +01:00 |
|
Florent Kermarrec
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d20b9c2221
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uart: pass *args, **kwargs to sim phy
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2015-03-06 12:08:10 +01:00 |
|
Florent Kermarrec
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af66ca7bad
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uart: add phy autodetect function
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2015-03-06 10:19:29 +01:00 |
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Florent Kermarrec
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95fa753149
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liteeth: add phy autodetect function (phy can still be instanciated directly)
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2015-03-06 10:10:34 +01:00 |
|
Florent Kermarrec
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bee8ccf6c7
|
soc: enforce cpu_reset_address to 0 when with_rom is True
|
2015-03-06 08:21:16 +01:00 |
|
Florent Kermarrec
|
2b9397ff5b
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targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
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2015-03-06 07:56:45 +01:00 |
|
Florent Kermarrec
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52f1c45407
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LiteXXX cores: fix test_reg.py
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2015-03-04 23:13:14 +01:00 |
|
Sebastien Bourdeauducq
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60e87f6e87
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Merge branch 'master' of https://github.com/m-labs/misoc
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2015-03-04 00:46:41 +00:00 |
|
Sebastien Bourdeauducq
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073641faa1
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litesata: fix permissions and imports
|
2015-03-04 00:46:24 +00:00 |
|
Florent Kermarrec
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200791c81d
|
uart: generate ack for rx (serialboot OK with sim)
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2015-03-04 00:57:37 +01:00 |
|
Florent Kermarrec
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7c058a52c9
|
com/spi: use .format in tb
|
2015-03-03 10:44:05 +01:00 |
|
Florent Kermarrec
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1d4dc45436
|
LiteXXX cores: use format in prints
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2015-03-03 10:29:28 +01:00 |
|
Florent Kermarrec
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f27e7a4b22
|
litesata: remove unneeded clock constraint
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2015-03-03 10:24:05 +01:00 |
|
Florent Kermarrec
|
0bcd6daf63
|
soc: remove is_sim function
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2015-03-03 10:15:11 +01:00 |
|
Florent Kermarrec
|
905be50451
|
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
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2015-03-03 09:55:25 +01:00 |
|
Florent Kermarrec
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9210272356
|
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
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2015-03-03 09:23:21 +01:00 |
|
Florent Kermarrec
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2f7206b386
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sdram: revert use of scalar values for DFIInjector
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2015-03-03 09:09:54 +01:00 |
|
Florent Kermarrec
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9df60bf98e
|
lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
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2015-03-03 09:02:53 +01:00 |
|
Sebastien Bourdeauducq
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ff29c86fe1
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litesata/kc705: use FMC pin names
|
2015-03-03 01:02:50 +00:00 |
|
Sebastien Bourdeauducq
|
8e48502d03
|
spiflash: style
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2015-03-03 00:54:30 +00:00 |
|
Florent Kermarrec
|
410a162841
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sdram: disable by default bandwidth_measurement on lasmicon
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2015-03-02 19:53:16 +01:00 |
|
Florent Kermarrec
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473997df26
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cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
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2015-03-02 16:52:17 +01:00 |
|
Florent Kermarrec
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8280acd3a7
|
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
|
2015-03-02 12:17:49 +01:00 |
|
Florent Kermarrec
|
3465db25a7
|
soc/sdram: be more generic in naming
|
2015-03-02 11:55:28 +01:00 |
|
Florent Kermarrec
|
97331153e0
|
sdram: create core dir and move lasmicon/minicon in it
|
2015-03-02 11:38:22 +01:00 |
|
Florent Kermarrec
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de698c51e4
|
sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
|
2015-03-02 11:29:43 +01:00 |
|
Florent Kermarrec
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6b24562eea
|
sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
|
2015-03-02 10:59:43 +01:00 |
|
Florent Kermarrec
|
46020fd253
|
sdram: for now revert dat_ack change (it seems there is an small issue, will have a closer look)
|
2015-03-02 10:34:29 +01:00 |
|
Florent Kermarrec
|
c0b38e4905
|
sdram/lasmicon: create a separate file for the crossbar and remove it from lasmibus
|
2015-03-02 09:18:32 +01:00 |
|
Florent Kermarrec
|
7300879b7f
|
sdram: move dfii to phy
|
2015-03-02 09:08:28 +01:00 |
|
Florent Kermarrec
|
9ad05b21ca
|
sdram: fix remaining data_valid in dma_lasmi
|
2015-03-02 09:05:18 +01:00 |
|
Florent Kermarrec
|
88e7fa21e4
|
sdram: create test dir and move lasmicon/minicon tests to it
|
2015-03-02 08:42:55 +01:00 |
|
Florent Kermarrec
|
b305b7828a
|
sdram: create frontend dir and move dma_lasmi/memtest/wishbone2lasmi to it
|
2015-03-02 08:36:39 +01:00 |
|
Florent Kermarrec
|
6d83a112e6
|
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
|
2015-03-01 22:04:27 +01:00 |