Florent Kermarrec
43429560d4
soc/integration/soc_core: add integrated_rom_init to allow initializing rom with custom code
2017-12-08 10:18:01 +01:00
Florent Kermarrec
284b16e2c1
soc/integration/soc_core: make nmi interrupt optional
2017-12-03 23:07:41 +01:00
Florent Kermarrec
c1eba9a6cc
soc/integration: add integrated_main_ram_init parameter to allow using main_ram with pre-initialized firmware
2017-11-24 13:16:58 +01:00
Florent Kermarrec
831b489fd3
soc/interconnect/stream: fix specific cases for last/first signal in UpConverter
2017-11-23 17:58:02 +01:00
Florent Kermarrec
c3d902ef42
soc/software/bios/sdram: add Kintex Ultrascale support
2017-11-08 12:59:38 +01:00
Florent Kermarrec
2665a83288
soc/interconnect/stream: expose depth on SyncFIFO
2017-10-30 22:56:09 +01:00
Tim 'mithro' Ansell
56ef229029
Make the interrupt dicts read only.
2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
295e78ee9e
Make it harder to have conflicting interrupts.
2017-10-29 19:45:52 -07:00
Tim 'mithro' Ansell
73e0036b99
Change the default IRQs.
...
* Reserve IRQ 0 to be used as a "non-maskable interrupt" (NMI) in the
future.
* Use IRQ 2 for the LiteX. This matches the standard mor1k config which
connects the UART to IRQ 2.
This change is needed for Linux running on LiteX as it gets grumpy with
using IRQ 0 for anything other other than an NMI.
2017-10-29 19:45:52 -07:00
Florent Kermarrec
db6c88bbef
soc/interconnect/stream: don't use reset less on last and first signals (not reseting these signals can cause troubles in some specific cases)
2017-10-12 11:30:56 +02:00
Tim 'mithro' Ansell
279ec488e3
bios: Print location jumping too.
...
Makes it easier to understand what is happening (and that the BIOS is
jumping to the right place).
2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
8152673d18
common: Compile with debugging symbols on.
...
Debugging symbols are useful when using GDB :-)
2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
b1b6a74170
or1k: Use EXCEPTION_STACK_SIZE of 256bytes.
...
or1k defines a 128 byte "red zone" after the stack that can not be
touched by the exception handler.
We also need 128 bytes to store the 32 registers.
2017-10-06 20:38:44 +11:00
Tim 'mithro' Ansell
07a9df3586
bios: Declare dependency on linked in .a files.
2017-10-06 20:38:44 +11:00
Florent Kermarrec
ba1bf20f37
soc/cores: add cordic
2017-09-29 12:07:43 +02:00
enjoy-digital
878380abba
Merge pull request #28 from enjoy-digital/eb-docs-2
...
More docs for etherbone packet fields.
2017-09-26 12:33:57 +02:00
Florent Kermarrec
2a8f6edded
soc/integration/soc_core: add ident_version parameter to allow adding soc version to identifier
2017-09-06 15:39:54 +02:00
Tim Ansell
3a656c61d9
More docs for etherbone packet fields.
...
Info comes from http://www.ohwr.org/attachments/1669/spec.pdf dated 24 July 2012
2017-09-01 23:57:34 +10:00
Tim Ansell
c125ea6440
Adding a little docs to field descriptions.
2017-09-01 23:27:58 +10:00
Florent Kermarrec
8f3dcf90ab
soc/software/bios/sdram: add optional memtest debug traces
2017-08-18 09:42:27 +02:00
Florent Kermarrec
c02de1632b
soc/cores: fix vivado issue with SPIRegister (at least with Vivado 2017.x+, mosi was not generated correctly), create cs_n signal if pads does not exists
2017-07-27 18:22:01 +02:00
Florent Kermarrec
04646b24ed
soc/interconnect/stream: fix make_m2s for reset_less
2017-07-24 18:18:35 +02:00
Florent Kermarrec
756554371a
soc/tools/remote/litex_server: allow multiple instance of server
2017-07-19 21:18:12 +02:00
Florent Kermarrec
d05d170b75
soc/integration/cpu_interface: do not generate constant access functions when with_access_functions is set to False
2017-07-19 12:18:35 +02:00
Florent Kermarrec
20c859d45c
soc/tools/remote/etherbone: speed optimization (~20/30%)
2017-07-17 00:25:58 +02:00
Florent Kermarrec
bdea4152e3
soc/core/uart: add UartStub to enable fast simulation with cpu
2017-07-06 19:19:10 +02:00
Florent Kermarrec
c6f6d7b491
soc/interconnect/wishbonebridge: reset_less optimizations
2017-06-30 19:41:14 +02:00
Florent Kermarrec
7fcdd94cd4
soc/interconnect/stream_packet: reset_less optimizations
2017-06-30 19:40:54 +02:00
Florent Kermarrec
227b14c3f3
soc/interconnect/stream: improve reset_less support for streams
2017-06-30 19:40:17 +02:00
Florent Kermarrec
f5a971a8d8
soc/interconnect/stream: use reset_less attr of signal for payload and param
2017-06-28 23:10:45 +02:00
Florent Kermarrec
4d664730fe
soc/software/libbase: fix get_ident
2017-06-28 18:10:56 +02:00
Florent Kermarrec
1364ac3657
soc/cores/identifier: append 0 to contents to indicate end of string
2017-06-22 17:53:19 +02:00
Florent Kermarrec
f720ef5631
soc/tools: simplify litex_server usage and integrage udp, pcie
2017-06-22 11:30:33 +02:00
Florent Kermarrec
41a91829eb
soc/tools: syntax fix on comm_pcie, import in __init__.py
2017-06-22 11:29:57 +02:00
Florent Kermarrec
c82c1d103f
soc/tools: fix debug prints of comm_pcie
2017-06-22 10:33:08 +02:00
Florent Kermarrec
684ae45dbe
soc/tools: remove csr builder from comm_udp (we should use litex_server)
2017-06-22 10:32:39 +02:00
Florent Kermarrec
c44a4b051f
soc/interconnect/stream: add first signal to streams (avoid over-complicated code in some cases)
2017-06-09 19:35:48 +02:00
Florent Kermarrec
c19c4b711b
soc/cores/identifier: remove additionnal first character
2017-06-08 14:15:27 +02:00
Florent Kermarrec
77732fca95
soc/cores/uart: add uart multiplexer
2017-06-05 19:36:30 +02:00
Florent Kermarrec
85aea62d74
soc/core: add frequency meter
2017-06-01 00:39:19 +02:00
Florent Kermarrec
4bc6cf6165
soc/cores: dna/xadc: add missing copyright
2017-05-16 21:18:32 +02:00
Florent Kermarrec
9350a7b5e6
soc/cores: add dna and xadc (for 7-series, add support for others fpgas?)
2017-05-16 21:02:33 +02:00
Florent Kermarrec
bedd428d9d
soc/integration/builder: remove error when compile_software=False and integrated ROM: when using compile_software=False user knows what he's doing.
2017-04-26 13:49:16 +02:00
Florent Kermarrec
c0800d25a6
soc/integration/builder.py: don't take care of ROM when compile_software is forced to False
2017-04-24 19:12:30 +02:00
Florent Kermarrec
b34f74397a
soc/cores: add code_8b10b from misoc
2017-04-19 11:05:21 +02:00
Florent Kermarrec
9cfc594280
soc/cores: move flash cores to cores directory
2017-04-19 10:58:15 +02:00
Florent Kermarrec
e1319924aa
soc: move uart to a single file
2017-04-19 10:37:59 +02:00
Florent Kermarrec
1acca39397
soc/cores: add new spi master, remove obsolete one
2017-04-19 10:22:35 +02:00
Florent Kermarrec
5efd6a8412
soc/interconnect/stream_packet.py: make error payload optional on Packetizer
2017-03-28 12:21:54 +02:00
Tim 'mithro' Ansell
4ee7019852
soc_core: Add CPU_RESET_ADDR as a constant.
...
So we can do a "soft reset" by jumping to this address.
2017-03-12 22:49:36 +11:00
