Commit Graph

7940 Commits

Author SHA1 Message Date
Florent Kermarrec 479773418d tools/litex_soc_gen: Add identifier, move wb_region to IOs and add optional debug. 2022-05-10 15:16:58 +02:00
Florent Kermarrec 51c5438c11 cpu/firev: Make name consistent with other CPUs. 2022-05-09 18:23:53 +02:00
enjoy-digital 7f703dd18f
Merge pull request #1293 from enjoy-digital/fhdl_namer_changes
FHDL Namer integration and memory .init naming improvements.
2022-05-09 18:22:42 +02:00
Florent Kermarrec 6d36fd2dda gen/fhdl/namer: Minor cleanup to ease readability. 2022-05-09 17:53:27 +02:00
Dolu1990 974d15d8c0
Merge pull request #1292 from zeldin/vexriscv_crt_fix
cpu/vexriscv: Fix compilation of crt0.S with new binutils.
2022-05-09 14:22:49 +02:00
Florent Kermarrec 2db57d4be3 interconnect: Add name parameter to Wishbone/AXI SRAMs nad use it in add_ram to improve generated memory names. 2022-05-09 10:29:15 +02:00
Florent Kermarrec 7370a9fe6f fhdl/memory/namer: Improve readability. 2022-05-09 10:22:48 +02:00
Marcus Comstedt a0f0ea4842 cpu/vexriscv: Fix compilation of crt0.S with new binutils.
The csrw opcode is no longer part of the "I" instruction set but has
been moved to a separate extension.  Enable that extension in crt0.S.
2022-05-08 18:54:23 +02:00
Florent Kermarrec 3a388d1f19 fhdl/memory: Prefix memory files with build name.
This simplify re-integrating pre-generated SubSoCs in a top level SoC.
2022-05-06 20:21:30 +02:00
Florent Kermarrec 7800858c7a gen/fhdl/namer: Cleanup & add comments on Namespace. 2022-05-06 20:07:35 +02:00
Florent Kermarrec 61eead5170 fhdl/memory/verilog: Rename ns -> namespace and minor cleanup. 2022-05-06 19:34:21 +02:00
Florent Kermarrec b83e84c78a gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names. 2022-05-06 16:04:24 +02:00
Florent Kermarrec 79d0e0916a CHANGES: Update. 2022-05-06 15:16:48 +02:00
Florent Kermarrec 3f101a3520 CHANGES: Update. 2022-05-06 13:43:39 +02:00
enjoy-digital a8c48b42f9
Merge pull request #1281 from antmicro/i2s_f4pga_fix
Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO to I2S
2022-05-06 09:10:22 +02:00
Florent Kermarrec 0a1ae7b413 setup.py: Expose litex_soc_gen and litex_periph_gen and sort console scripts. 2022-05-05 17:44:59 +02:00
Florent Kermarrec e8b6200225 tools: Add initial LiteX standalone SoC generator.
Allow generating standalone SoC with CPU/Peripherals that can be re-integrated in
external design or top level LiteX SoCs.

Example of of use:
python3 litex_soc_gen.py --cpu-type=vexriscv --bus-standard=wishbone --build
python3 litex_soc_gen.py --cpu-type=naxriscv --bus-standard=axi-lite --build
2022-05-05 17:36:34 +02:00
Florent Kermarrec e7cee80670 tools/litex_gen: Rename to litex_periph_gen to make it more explicit (And also to prepare for litex_soc_gen). 2022-05-05 17:36:22 +02:00
Florent Kermarrec 36ea82546f litex_setup: Allow specifying tag for --init --update.
Allow installing from release tags, ex to install 2022.04 from scratch:
./litex_setup.py --tag=2022.04 --init --install --user.

To update to 2022.04 from a previous installation:
./litex_setup.py --tag=2022.04 --update

To update to latest (dev):
./litex_setup.py --updatelitex_setup: Allow specifying tag for --init --update.
2022-05-04 19:26:22 +02:00
Florent Kermarrec a4cc859df0 CHANGES: Do 2022.04 release. 2022-05-03 13:09:30 +02:00
Florent Kermarrec 17b6f792c7 tools/litex_client: Fix read/write when address is directly specified. 2022-05-03 10:05:04 +02:00
Florent Kermarrec 8f63a64a86 cores/hyperbus: Simplify #1288 and add parameter retro-compatibility.
sys_clk_freq is set to 10e6 when passed to None.
2022-05-02 17:24:35 +02:00
enjoy-digital 25e7569cd1
Merge pull request #1288 from fjullien/hyperram_timeout
Hyperram timeout and cyc
2022-05-02 16:30:58 +02:00
Florent Kermarrec c12bdf5454 CHANGES: Update. 2022-05-02 14:18:12 +02:00
Florent Kermarrec cd589846c4 CONTRIBUTORS: Update. 2022-05-02 14:01:41 +02:00
Franck Jullien a66af6343e hyperbus: check if cyc is active during every state 2022-04-28 23:05:58 +02:00
Franck Jullien 5220984df8 hyperbus: add a timeout for long bursts 2022-04-28 23:05:58 +02:00
Robert Szczepanski d5878050b3 cores: i2s: Use FIFOSyncMacro if not built with Vivado 2022-04-27 10:53:52 +02:00
Robert Szczepanski 22abe1d543 Add tests for FIFOSyncMacro 2022-04-27 10:53:52 +02:00
Robert Szczepanski c584cb3fa7 Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO 2022-04-27 10:53:52 +02:00
enjoy-digital 665367fe67
Merge pull request #1284 from smunaut/bist-overflow
fix overflow in BIST
2022-04-27 10:08:59 +02:00
Sylvain Munaut 6ec7a24731 software/liblitedram: Fixup overflow in BIST speed math
With decent burst length, fast RAM and fast clock rate,
the intermediate result can easily overflow 32 bits.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-04-26 23:33:08 +02:00
enjoy-digital 3959ca39d4
Merge pull request #1282 from cklarhorst/master
software/bios: Fix build error for targets with sdcard but without main_ram_base
2022-04-25 19:26:47 +02:00
Florent Kermarrec 63cda6c7b9 soc/add_ethernet: soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width. 2022-04-25 18:44:52 +02:00
Florent Kermarrec bdbb6c0b3f soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width. 2022-04-25 17:49:57 +02:00
Christian Klarhorst 6ca890ebc0 software/bios: Fix build error for targets with sdcard but without main_ram_base
sdcardboot_from_bin assumes that the MAIN_RAM_BASE is set which is not always
the case. This commit deactivates the sdcardboot_from_bin support for targets
without main-ram. In those cases, the boot_from_json method can still be used.
2022-04-25 16:49:59 +02:00
Florent Kermarrec edd98c23cb interconnect/packet/PacketFIFO: +1 on param_depth to allow dequeuing current while equeuing next. 2022-04-25 15:48:05 +02:00
Florent Kermarrec 625261c693 cores/video: Fix depth checks that have to be done in Python, not in logic.
Fixes https://github.com/enjoy-digital/litex/issues/1198.
2022-04-22 19:36:46 +02:00
Florent Kermarrec 1a713225ea cpu/cortex_m1/m3: Add gcc_flags property and only keep UART_POLLING mode for now. 2022-04-22 18:44:49 +02:00
Florent Kermarrec 38fbe8f4ca cores/cpu: Add category property (hardcore or softcore) and improve CPU listing. 2022-04-22 18:00:44 +02:00
Florent Kermarrec b607de473d cpu/cortex_m3: Review/Cleanup (Apply similar changes than for Cortex-M1). 2022-04-22 17:03:02 +02:00
Florent Kermarrec 2508b16f38 cpu/cortex_m1: Minor cosmetic changes. 2022-04-22 17:02:05 +02:00
Ilia Sergachev 1211cb6ab5 cpu: Add initial Cortex-M3 support.
can be test with targets from LiteX-Boards and Cortex-M3 sources in execution path:

python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m3 --sy-clk-freq=50e6 --build --load

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr 22 2022 16:23:30
 BIOS CRC passed (b390faf0)

 LiteX git sha1: 99a03426

--=============== SoC ==================--
CPU:		ARM Cortex-M3 @ 50MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		262144KiB 16-bit @ 400MT/s (CL-7 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x10000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |11111111111111111111111111100000| delays: 13+-13
  m0, b02: |00000000000000000000000000001111| delays: 30+-02
  m0, b03: |00000000000000000000000000000000| delays: -
  m0, b04: |00000000000000000000000000000000| delays: -
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b01 delays: 13+-13
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |11111111111111111111111111000000| delays: 13+-13
  m1, b02: |00000000000000000000000000000111| delays: 31+-02
  m1, b03: |00000000000000000000000000000000| delays: -
  m1, b04: |00000000000000000000000000000000| delays: -
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b01 delays: 13+-13
Switching SDRAM to hardware control.
Memtest at 0x10000000 (2.0MiB)...
  Write: 0x10000000-0x10200000 2.0MiB
   Read: 0x10000000-0x10200000 2.0MiB
Memtest OK
Memspeed at 0x10000000 (Sequential, 2.0MiB)...
  Write speed: 9.7MiB/s
   Read speed: 12.6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
2022-04-22 16:41:51 +02:00
Florent Kermarrec 99a034268d cpu/naxriscv: Remove Wishbone import/comments (Now fully AXI/AXI-Lite). 2022-04-22 16:16:45 +02:00
Florent Kermarrec 31cfe137d1 cpu/cortex_m1/core: Review/Cleanup.
- Increase similarities with other CPUs.
- Classify instance signals.
- Use Open instead of Signal on open ports.
- Switch pbus to AXILite instead of Wishbone.
- Directly connect AXI ports.
- Rename connect_jtag to add_jtag.
2022-04-22 16:15:39 +02:00
Ilia Sergachev 51eb310b0e cpu: Add initial Cortex-M1 support.
Can be tested with targets from LiteX-Boards and Cortex-M1 sources in execution path:

python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m1 --build --load

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr 22 2022 15:04:52
 BIOS CRC passed (5773c241)

 LiteX git sha1: 6b3a5412

--=============== SoC ==================--
CPU:		ARM Cortex-M1 @ 100MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		262144KiB 16-bit @ 800MT/s (CL-7 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x10000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |11111111110000000000000000000000| delays: 05+-05
  m0, b03: |00000000000011111111111111000000| delays: 19+-07
  m0, b04: |00000000000000000000000000011111| delays: 30+-02
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b03 delays: 19+-07
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |00000000000000000000000000000000| delays: -
  m1, b02: |11111111110000000000000000000000| delays: 05+-05
  m1, b03: |00000000000011111111111111000000| delays: 19+-07
  m1, b04: |00000000000000000000000000001111| delays: 30+-02
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b03 delays: 19+-07
Switching SDRAM to hardware control.
Memtest at 0x10000000 (2.0MiB)...
  Write: 0x10000000-0x10200000 2.0MiB
   Read: 0x10000000-0x10200000 2.0MiB
Memtest OK
Memspeed at 0x10000000 (Sequential, 2.0MiB)...
  Write speed: 16.5MiB/s
   Read speed: 19.3MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
2022-04-22 15:22:23 +02:00
Ilia Sergachev 016e1abcff software/libcompiler_rt: Fix compilation for ARM/Cortex-M1. 2022-04-22 15:16:55 +02:00
Florent Kermarrec e2bf77b0e3 integration/soc: Fix comment typo. 2022-04-22 15:12:49 +02:00
Florent Kermarrec 6b3a541241 xilinx/vivado: Differentiate IOs and internal nets when applying timing constraints.
Use get_nets on internal nets, get_ports on IOs.
2022-04-21 18:15:05 +02:00
Florent Kermarrec 08e9cfcd86 soc/usb_acm: Move clone of ValentyUSB to LiteX instead of doing it in each LiteX-Boards target. 2022-04-21 15:43:00 +02:00