479773418d
tools/litex_soc_gen: Add identifier, move wb_region to IOs and add optional debug.
2022-05-10 15:16:58 +02:00
51c5438c11
cpu/firev: Make name consistent with other CPUs.
2022-05-09 18:23:53 +02:00
7f703dd18f
Merge pull request #1293 from enjoy-digital/fhdl_namer_changes
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FHDL Namer integration and memory .init naming improvements.
2022-05-09 18:22:42 +02:00
6d36fd2dda
gen/fhdl/namer: Minor cleanup to ease readability.
2022-05-09 17:53:27 +02:00
974d15d8c0
Merge pull request #1292 from zeldin/vexriscv_crt_fix
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cpu/vexriscv: Fix compilation of crt0.S with new binutils.
2022-05-09 14:22:49 +02:00
2db57d4be3
interconnect: Add name parameter to Wishbone/AXI SRAMs nad use it in add_ram to improve generated memory names.
2022-05-09 10:29:15 +02:00
7370a9fe6f
fhdl/memory/namer: Improve readability.
2022-05-09 10:22:48 +02:00
a0f0ea4842
cpu/vexriscv: Fix compilation of crt0.S with new binutils.
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The csrw opcode is no longer part of the "I" instruction set but has
been moved to a separate extension. Enable that extension in crt0.S.
2022-05-08 18:54:23 +02:00
3a388d1f19
fhdl/memory: Prefix memory files with build name.
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This simplify re-integrating pre-generated SubSoCs in a top level SoC.
2022-05-06 20:21:30 +02:00
7800858c7a
gen/fhdl/namer: Cleanup & add comments on Namespace.
2022-05-06 20:07:35 +02:00
61eead5170
fhdl/memory/verilog: Rename ns -> namespace and minor cleanup.
2022-05-06 19:34:21 +02:00
b83e84c78a
gen/fhdl: Integrate namer from Migen to give us more flexibility on generated verilog names.
2022-05-06 16:04:24 +02:00
79d0e0916a
CHANGES: Update.
2022-05-06 15:16:48 +02:00
3f101a3520
CHANGES: Update.
2022-05-06 13:43:39 +02:00
a8c48b42f9
Merge pull request #1281 from antmicro/i2s_f4pga_fix
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Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO to I2S
2022-05-06 09:10:22 +02:00
0a1ae7b413
setup.py: Expose litex_soc_gen and litex_periph_gen and sort console scripts.
2022-05-05 17:44:59 +02:00
e8b6200225
tools: Add initial LiteX standalone SoC generator.
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Allow generating standalone SoC with CPU/Peripherals that can be re-integrated in
external design or top level LiteX SoCs.
Example of of use:
python3 litex_soc_gen.py --cpu-type=vexriscv --bus-standard=wishbone --build
python3 litex_soc_gen.py --cpu-type=naxriscv --bus-standard=axi-lite --build
2022-05-05 17:36:34 +02:00
e7cee80670
tools/litex_gen: Rename to litex_periph_gen to make it more explicit (And also to prepare for litex_soc_gen).
2022-05-05 17:36:22 +02:00
36ea82546f
litex_setup: Allow specifying tag for --init --update.
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Allow installing from release tags, ex to install 2022.04 from scratch:
./litex_setup.py --tag=2022.04 --init --install --user.
To update to 2022.04 from a previous installation:
./litex_setup.py --tag=2022.04 --update
To update to latest (dev):
./litex_setup.py --updatelitex_setup: Allow specifying tag for --init --update.
2022-05-04 19:26:22 +02:00
a4cc859df0
CHANGES: Do 2022.04 release.
2022-05-03 13:09:30 +02:00
17b6f792c7
tools/litex_client: Fix read/write when address is directly specified.
2022-05-03 10:05:04 +02:00
8f63a64a86
cores/hyperbus: Simplify #1288 and add parameter retro-compatibility.
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sys_clk_freq is set to 10e6 when passed to None.
2022-05-02 17:24:35 +02:00
25e7569cd1
Merge pull request #1288 from fjullien/hyperram_timeout
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Hyperram timeout and cyc
2022-05-02 16:30:58 +02:00
c12bdf5454
CHANGES: Update.
2022-05-02 14:18:12 +02:00
cd589846c4
CONTRIBUTORS: Update.
2022-05-02 14:01:41 +02:00
a66af6343e
hyperbus: check if cyc is active during every state
2022-04-28 23:05:58 +02:00
5220984df8
hyperbus: add a timeout for long bursts
2022-04-28 23:05:58 +02:00
d5878050b3
cores: i2s: Use FIFOSyncMacro if not built with Vivado
2022-04-27 10:53:52 +02:00
22abe1d543
Add tests for FIFOSyncMacro
2022-04-27 10:53:52 +02:00
c584cb3fa7
Add LiteX equivalent of Xilinx FIFO_SYNC_MACRO
2022-04-27 10:53:52 +02:00
665367fe67
Merge pull request #1284 from smunaut/bist-overflow
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fix overflow in BIST
2022-04-27 10:08:59 +02:00
6ec7a24731
software/liblitedram: Fixup overflow in BIST speed math
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With decent burst length, fast RAM and fast clock rate,
the intermediate result can easily overflow 32 bits.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2022-04-26 23:33:08 +02:00
3959ca39d4
Merge pull request #1282 from cklarhorst/master
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software/bios: Fix build error for targets with sdcard but without main_ram_base
2022-04-25 19:26:47 +02:00
63cda6c7b9
soc/add_ethernet: soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width.
2022-04-25 18:44:52 +02:00
bdbb6c0b3f
soc/add_etherbone: Add data_width parameter and allow 8-bit/32-bit core data_width.
2022-04-25 17:49:57 +02:00
6ca890ebc0
software/bios: Fix build error for targets with sdcard but without main_ram_base
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sdcardboot_from_bin assumes that the MAIN_RAM_BASE is set which is not always
the case. This commit deactivates the sdcardboot_from_bin support for targets
without main-ram. In those cases, the boot_from_json method can still be used.
2022-04-25 16:49:59 +02:00
edd98c23cb
interconnect/packet/PacketFIFO: +1 on param_depth to allow dequeuing current while equeuing next.
2022-04-25 15:48:05 +02:00
625261c693
cores/video: Fix depth checks that have to be done in Python, not in logic.
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Fixes https://github.com/enjoy-digital/litex/issues/1198 .
2022-04-22 19:36:46 +02:00
1a713225ea
cpu/cortex_m1/m3: Add gcc_flags property and only keep UART_POLLING mode for now.
2022-04-22 18:44:49 +02:00
38fbe8f4ca
cores/cpu: Add category property (hardcore or softcore) and improve CPU listing.
2022-04-22 18:00:44 +02:00
b607de473d
cpu/cortex_m3: Review/Cleanup (Apply similar changes than for Cortex-M1).
2022-04-22 17:03:02 +02:00
2508b16f38
cpu/cortex_m1: Minor cosmetic changes.
2022-04-22 17:02:05 +02:00
1211cb6ab5
cpu: Add initial Cortex-M3 support.
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can be test with targets from LiteX-Boards and Cortex-M3 sources in execution path:
python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m3 --sy-clk-freq=50e6 --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Apr 22 2022 16:23:30
BIOS CRC passed (b390faf0)
LiteX git sha1: 99a03426
2022-04-22 16:41:51 +02:00
99a034268d
cpu/naxriscv: Remove Wishbone import/comments (Now fully AXI/AXI-Lite).
2022-04-22 16:16:45 +02:00
31cfe137d1
cpu/cortex_m1/core: Review/Cleanup.
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- Increase similarities with other CPUs.
- Classify instance signals.
- Use Open instead of Signal on open ports.
- Switch pbus to AXILite instead of Wishbone.
- Directly connect AXI ports.
- Rename connect_jtag to add_jtag.
2022-04-22 16:15:39 +02:00
51eb310b0e
cpu: Add initial Cortex-M1 support.
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Can be tested with targets from LiteX-Boards and Cortex-M1 sources in execution path:
python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m1 --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Apr 22 2022 15:04:52
BIOS CRC passed (5773c241)
LiteX git sha1: 6b3a5412
2022-04-22 15:22:23 +02:00
016e1abcff
software/libcompiler_rt: Fix compilation for ARM/Cortex-M1.
2022-04-22 15:16:55 +02:00
e2bf77b0e3
integration/soc: Fix comment typo.
2022-04-22 15:12:49 +02:00
6b3a541241
xilinx/vivado: Differentiate IOs and internal nets when applying timing constraints.
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Use get_nets on internal nets, get_ports on IOs.
2022-04-21 18:15:05 +02:00
08e9cfcd86
soc/usb_acm: Move clone of ValentyUSB to LiteX instead of doing it in each LiteX-Boards target.
2022-04-21 15:43:00 +02:00
Florent Kermarrec
Dolu1990
Marcus Comstedt
Franck Jullien
Robert Szczepanski
Sylvain Munaut
Christian Klarhorst
Ilia Sergachev