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Author SHA1 Message Date
Florent Kermarrec
2508b16f38 cpu/cortex_m1: Minor cosmetic changes. 2022-04-22 17:02:05 +02:00
Ilia Sergachev
1211cb6ab5 cpu: Add initial Cortex-M3 support. 
can be test with targets from LiteX-Boards and Cortex-M3 sources in execution path:

python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m3 --sy-clk-freq=50e6 --build --load

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr 22 2022 16:23:30
 BIOS CRC passed (b390faf0)

 LiteX git sha1: 99a03426

--=============== SoC ==================--
CPU:		ARM Cortex-M3 @ 50MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		262144KiB 16-bit @ 400MT/s (CL-7 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x10000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |11111111111111111111111111100000| delays: 13+-13
  m0, b02: |00000000000000000000000000001111| delays: 30+-02
  m0, b03: |00000000000000000000000000000000| delays: -
  m0, b04: |00000000000000000000000000000000| delays: -
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b01 delays: 13+-13
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |11111111111111111111111111000000| delays: 13+-13
  m1, b02: |00000000000000000000000000000111| delays: 31+-02
  m1, b03: |00000000000000000000000000000000| delays: -
  m1, b04: |00000000000000000000000000000000| delays: -
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b01 delays: 13+-13
Switching SDRAM to hardware control.
Memtest at 0x10000000 (2.0MiB)...
  Write: 0x10000000-0x10200000 2.0MiB
   Read: 0x10000000-0x10200000 2.0MiB
Memtest OK
Memspeed at 0x10000000 (Sequential, 2.0MiB)...
  Write speed: 9.7MiB/s
   Read speed: 12.6MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2022-04-22 16:41:51 +02:00
Florent Kermarrec
99a034268d cpu/naxriscv: Remove Wishbone import/comments (Now fully AXI/AXI-Lite). 2022-04-22 16:16:45 +02:00
Florent Kermarrec
31cfe137d1 cpu/cortex_m1/core: Review/Cleanup. 
- Increase similarities with other CPUs.
- Classify instance signals.
- Use Open instead of Signal on open ports.
- Switch pbus to AXILite instead of Wishbone.
- Directly connect AXI ports.
- Rename connect_jtag to add_jtag.
 2022-04-22 16:15:39 +02:00
Ilia Sergachev
51eb310b0e cpu: Add initial Cortex-M1 support. 
Can be tested with targets from LiteX-Boards and Cortex-M1 sources in execution path:

python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m1 --build --load

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr 22 2022 15:04:52
 BIOS CRC passed (5773c241)

 LiteX git sha1: 6b3a5412

--=============== SoC ==================--
CPU:		ARM Cortex-M1 @ 100MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB
L2:		8KiB
SDRAM:		262144KiB 16-bit @ 800MT/s (CL-7 CWL-5)

--========== Initialization ============--
Initializing SDRAM @0x10000000...
Switching SDRAM to software control.
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |11111111110000000000000000000000| delays: 05+-05
  m0, b03: |00000000000011111111111111000000| delays: 19+-07
  m0, b04: |00000000000000000000000000011111| delays: 30+-02
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b03 delays: 19+-07
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |00000000000000000000000000000000| delays: -
  m1, b02: |11111111110000000000000000000000| delays: 05+-05
  m1, b03: |00000000000011111111111111000000| delays: 19+-07
  m1, b04: |00000000000000000000000000001111| delays: 30+-02
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b03 delays: 19+-07
Switching SDRAM to hardware control.
Memtest at 0x10000000 (2.0MiB)...
  Write: 0x10000000-0x10200000 2.0MiB
   Read: 0x10000000-0x10200000 2.0MiB
Memtest OK
Memspeed at 0x10000000 (Sequential, 2.0MiB)...
  Write speed: 16.5MiB/s
   Read speed: 19.3MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
 2022-04-22 15:22:23 +02:00
Ilia Sergachev
016e1abcff software/libcompiler_rt: Fix compilation for ARM/Cortex-M1. 2022-04-22 15:16:55 +02:00
Florent Kermarrec
e2bf77b0e3 integration/soc: Fix comment typo. 2022-04-22 15:12:49 +02:00
Florent Kermarrec
6b3a541241 xilinx/vivado: Differentiate IOs and internal nets when applying timing constraints. 
Use get_nets on internal nets, get_ports on IOs.
 2022-04-21 18:15:05 +02:00
Florent Kermarrec
08e9cfcd86 soc/usb_acm: Move clone of ValentyUSB to LiteX instead of doing it in each LiteX-Boards target. 2022-04-21 15:43:00 +02:00
Dolu1990
ca6378a207 cpu/NaxRiscv: Improve place and route timings robustness 2022-04-20 15:13:09 +02:00
Florent Kermarrec
ff6e7bd6ad cores/uart/Stream2Wishbone: Add asserts on data_width/address_width. 2022-04-20 11:01:21 +02:00
enjoy-digital
5e451d68f7
Merge pull request #1277 from trabucayre/uart_fix_Stream2Wishbone_v2 
Uart fix stream2 wishbone v2
 2022-04-20 10:56:38 +02:00
Florent Kermarrec
4e5d1848cc integration/soc/cpu: Improve cpu-type/cpu-variant listing. 2022-04-20 10:37:03 +02:00
Florent Kermarrec
3dbe349dd9 liblitesata/sata_init: Add SATA Read check (Seems to be required with some disks). 2022-04-15 18:01:26 +02:00
Gwenhael Goavec-Merou
a988712974 soc/cores/uart:Stream2Wishbone: remove no more needed data_width/address_width equality test 2022-04-15 17:43:50 +02:00
Gwenhael Goavec-Merou
3cb34e7951 soc/cores/uart:Stream2Wishbone: supress data/address egality assert 2022-04-15 17:41:34 +02:00
Florent Kermarrec
557ebcedfb liblitesata/sata_init: Always reinitialize core on call (Even when already ready). 2022-04-15 13:53:18 +02:00
Florent Kermarrec
ceb25445d2 wishbone/sram/burst: First review/Minor cleanups. 2022-04-15 09:03:12 +02:00
enjoy-digital
9c4778b2c1
Merge pull request #1267 from antmicro/wb-sram-inc-burst 
soc/interconnect/wishbone: Add incrementing address burst mode to SRAM
 2022-04-15 08:47:42 +02:00
Florent Kermarrec
8b2fc201cf soc/cores/uart: Add assert data_width == address_width to prevent building broken logic and pass data_width/address_width to Wishbone. 2022-04-15 08:39:45 +02:00
enjoy-digital
fac39c8210
Merge pull request #1275 from fjullien/efinix_ifacewriter_add_gpio_options 
Efinix ifacewriter add gpio options
 2022-04-15 08:19:57 +02:00
enjoy-digital
08cd4803f3
Merge pull request #1274 from fjullien/fix_efinix_pll 
Fix efinix pll
 2022-04-15 08:19:18 +02:00
Franck Jullien
e86c06c9ff efinix:clock: improve logging informations 2022-04-14 10:48:51 +02:00
Franck Jullien
25b4eb7b0b efinix: dont print info in get_pll_resource 2022-04-14 10:48:51 +02:00
Franck Jullien
5f9d943d36 efinix: get_free_pll_resource needs to call get_pll_resource 2022-04-14 10:48:51 +02:00
Franck Jullien
66e49249cc efinix:ifacewriter: add out_clk_inv and in_clk_inv to gpio block 2022-04-14 10:42:55 +02:00
Franck Jullien
78c35365e8 efinix:ifacewriter: add in_reg and out_reg to gpio block 2022-04-14 10:42:48 +02:00
Florent Kermarrec
63356b8187 cpu/naxriscv: Minor cleanups. 2022-04-14 10:12:45 +02:00
Florent Kermarrec
0a738002e0 openocd/jtag: Add JTAG-UART/JTABBone support to Zynq7000/ZynqMPSoC and define all Xilinx IRs for USERX. 
Thanks @smunaut for the initial investigation/implementation. The changes have been minimized to:
- Adding an optional delay in TDI: On Zynq devices, TDI is delayed by 1 TCK to bypass the PS tap.
- Avoiding OpenOCD's -endstate DRPAUSE on Xilinx that does not seem required.
 2022-04-14 09:51:03 +02:00
Dolu1990
be43ef6424 cpu/NaxRiscv: Now support reset from the jtag 2022-04-12 19:38:36 +02:00
Rafal Kolucki
8c1bc139ab soc/interconnect/wishbone: Cleanup in burst cycles support logic 2022-04-12 15:32:29 +02:00
Rafal Kolucki
ad46a57403 test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle 2022-04-12 14:06:22 +02:00
Rafal Kolucki
cdd216f692 test/test_wishbone: Add basic test for SRAM with burst cycles support 
Tests incrementing address burst cycle with linear and wrapped increments.
Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.
 2022-04-12 14:06:22 +02:00
Rafal Kolucki
c00ca99ea9 soc/interconnect/wishbone: Add burst params to Interface test functions 
This commit also replaces hardcoded CTI signal values with constants.
 2022-04-12 14:06:22 +02:00
Rafal Kolucki
83ea56aeee soc/interconnect/wishbone: Move burst cycles support option to SoCBusHandler/SoC classes 2022-04-12 14:06:22 +02:00
Rafal Kolucki
ca78f799e1 soc/integration/soc_core: Add SRAM/ROM burst cycles support switch 2022-04-12 14:06:22 +02:00
Rafal Kolucki
54f897f446 soc/interconnect/wishbone: Make burst cycles support in SRAM optional 2022-04-12 14:06:22 +02:00
Rafal Kolucki
8ef51a00ee soc/interconnect/wishbone: Add incrementing burst cycles support to SRAM 
This commit adds support for incrementing burst cycles in SRAM peripheral.
By default it's enabled, but can be disabled by passing `burst=False`
to the class while initializing, if it won't be useful for created design
(e.g. no Wishbone bus masters with burst support).
 2022-04-12 14:06:22 +02:00
Florent Kermarrec
7416943f9c cores/usb_fifo: Re-implement FT245PHYSynchronous, passing simple tests on FT601/LimeSDRMini-V2.0. 2022-04-11 19:23:58 +02:00
Florent Kermarrec
7187ac22e4 interconnect/axi: Add AXSIZE dict definition. 2022-04-11 19:20:22 +02:00
Florent Kermarrec
1989d85b91 software/libbase/i2c/i2c_poll: Also test for write when polling since some I2C devices do not respond to read or require a specific protocol. 2022-04-11 09:52:00 +02:00
Florent Kermarrec
9806f76619 soc/build: Remove Migen Git SHA1 from auto-generated headers/bios (Hasn't been useful). 2022-04-11 09:50:00 +02:00
Florent Kermarrec
c834600a5a naxriscv/core: Cleanup ident. 2022-04-08 18:53:46 +02:00
Dolu1990
c4dba614a6 cpu/naxriscv Got soft jtag tap and hard jtag tap with tunneling to work on hardware 2022-04-08 17:12:39 +02:00
Florent Kermarrec
fa611ba809 software/demo: Update README.md. 2022-04-07 11:47:14 +02:00
Florent Kermarrec
5222e7fc1a software/demo: Add --mem parameter to allow specifying Memory region where code will be loaded/executed. 2022-04-07 11:22:12 +02:00
Florent Kermarrec
20c9bba8da software/demo: Fix some warnings. 2022-04-07 10:50:07 +02:00
Florent Kermarrec
8e1265113b software/demo/Makefile: Make it as much as possible similar to BIOS's Makefile. 2022-04-07 10:49:46 +02:00
Florent Kermarrec
b9fce9e1b2 soc/integration/builder: Add --no-compile argument to disable software and gateware compilation. 
Short equivalent of --no-compile-software --no-compile-gateware.
 2022-04-07 09:42:52 +02:00
Florent Kermarrec
f224036138 stream/ClockDomainCrossing: Revert with_common_rst to False by default (Previous behavior). 
This seems to cause issues in simulation on some cores, this will first have to be fixed before
using it as default. Cores requiring it will set it to True explicitly for now.
 2022-04-05 19:53:00 +02:00