Useful on small FPGAs to reduce resource usage: When enabling bus mastering,
the core is able to automatically read led values from the bus and can then
avoid the internal memory. This is particularly useful when reading values
from SPI Flash with a small "Player" core just updating the base address.
Add `reg-names` property, which facilitates cleaner probing
for the upstream Linux device driver. Also, add a reference
to the LiteX sys_clk, also for the benefit of the upstream
driver, which can't rely on the CPU frequency matching sys_clk.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Remove `bus-frequency` property from `soc` node. Instead,
create a separate `clocks` section containing a node to
represent the LiteX sys_clk, which may be referenced from
other peripherals if needed.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Removes a leftover debug message for validating correct XGMII IFG DIC
behavior. Useful for development, but gets annoying quickly while
running the simulation.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
Use the technology specific multiplier implementation when building for a
Xilinx platform.
This isn't understood by yosys so we can't use it when yosys is used for
synthesis.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Because XGMII only allows start of frame characters to be placed on lane
0 (first octet in a 32-bit XGMII bus word), when a packet's length % 4 !=
0, we can't transmit exactly 12 XGMII idle characters inter-frame gap
(the XGMII end of frame character counts towards the inter-frame gap,
while start of frame does not). Given we are required to transmit a
minimum of 12 bytes IFG, it's allowed to send packet length % 4 bytes
additional IFG bytes. However this would waste precious bandwidth
transmitting these characters.
Thus, 10Gbit/s Ethernet and above allow using the deficit idle count
mechanism. It allows to delete some idle characters, as long as an
average count of >= 12 bytes IFG is maintained. This is to be
implemented as a two bit counter as specified in IEEE802.3-2018,
section four, 46.3.1.4 Start control character alignment.
This commit optionally implements the deficit idle count algorithm as
described by Eric Lynskey of the UNH InterOperability Lab[1]. It may
not have much or any impact in the XGMII simulation when using a TAP
interface, however when connecting this simulation to another the DIC
mechanism is a valuable implementation for both saturating proper
10Gbit/s linerate and validating the LiteEth PHY (XGMII to stream)
converter implementation.
[1]: https://www.iol.unh.edu/sites/default/files/knowledgebase/10gec/10GbE_DIC.pdf
Signed-off-by: Leon Schuermann <leon@is.currently.online>
Franck Jullien
Florent Kermarrec
whitequark
Gabriel Somlo
Greg Davill
Ilia Sergachev
Tim Callahan
Ray Molenkamp
Andrew Dennison
Leon Schuermann
Joel Stanley
Andy Kitchen
Miodrag Milanovic