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4775 Commits

Author SHA1 Message Date
Florent Kermarrec 5dc440e80d csr: use IntEnum for CSRAccess 2019-09-16 08:36:25 +02:00
Florent Kermarrec d2646f138e csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful 2019-09-15 19:47:48 +02:00
Florent Kermarrec 8e14694eb5 csr/fields: document, add separators, 100 characters per line 2019-09-15 19:11:25 +02:00
Florent Kermarrec 4e84729cf9 csr/fields: add access parameter 2019-09-14 22:16:18 +02:00
Florent Kermarrec 23b01f8f02 csr/fields: add pulse mode support 2019-09-14 21:49:34 +02:00
Florent Kermarrec 8c080e5fb6 soc/interconnect/csr: add initial field support 2019-09-13 20:01:31 +02:00
Florent Kermarrec c120f6d457 build/openocd: add set_qe parameter to flash 
QE bit is not set on blank SPI flashes and need to be set when SPI X4 is enabled in the bistream to load the FPGA.
 2019-09-12 17:07:56 +02:00
Florent Kermarrec 6a0a1c9d87 tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) 2019-09-12 10:21:37 +02:00
Florent Kermarrec 16b6b357ca soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found 2019-09-11 18:30:28 +02:00
Florent Kermarrec 62f53d5035 soc/integration/builder: call do_exit with vns when build is done. 2019-09-10 12:41:05 +02:00
Florent Kermarrec cb5f1467cf Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-09-09 15:12:24 +02:00
Florent Kermarrec 004c96b508 soc/itnegration: update litedram 2019-09-09 15:12:08 +02:00
enjoy-digital a7b5c18523
Merge pull request #255 from sergachev/fix-crc32 
fix crc32
 2019-09-09 13:38:29 +02:00
Ilia Sergachev 2400f0f43d fix crc32 2019-09-09 13:19:43 +02:00
Florent Kermarrec 19f58dd971 interconnect/wishbone: add FlipFlop to allow UpConverter to be used 
Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up
 2019-09-09 11:47:36 +02:00
Florent Kermarrec bd6ec63be4 build/openocd: add stream method for JTAG UART 2019-09-06 11:57:18 +02:00
Florent Kermarrec b356204f95 soc_core: add JTAG UART support (uart_name="jtag_uart) 2019-09-06 11:56:42 +02:00
Florent Kermarrec d0ebbda4b3 soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) 2019-09-06 11:55:41 +02:00
Florent Kermarrec 2638393b53 soc_zynq: fix indent 2019-09-05 15:59:35 +02:00
Florent Kermarrec 9051cf97e4 soc_zynq: fix typo 2019-09-05 15:55:18 +02:00
Florent Kermarrec 67a09aef05 soc/interconnect/stream: add Monitor module 
Generic module to monitor endpoints activity: tokens/overflows/underflows that
can be plugged on a endpoint. Can be useful for various purpose:
- endpoint bandwidth calculation.
- underflows/overflows detection.
- etc...
 2019-09-05 11:54:14 +02:00
enjoy-digital 6f150a5626
Merge pull request #254 from mithro/crc-smaller 
Add @xobs' smaller CRC version
 2019-09-03 07:23:32 +02:00
Tim 'mithro' Ansell 2a41f0d2a4 Use `SMALL_CRC` to enable smaller CRC versions. 
@xobs created a smaller code size version of the CRC functions. Enable
these if someone uses the `SMALL_CRC` define.
 2019-09-02 14:48:30 -07:00
Tim 'mithro' Ansell 083337441a Remove extra whitespace. 2019-09-02 14:47:20 -07:00
Sean Cross c0e723868e libbase: crc16: commit smaller version of crc16 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:44:18 -07:00
Sean Cross a59d0efca0 libbase: crc32: add smaller version 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-02 14:44:18 -07:00
Tim Ansell 27c334d440
Merge pull request #252 from mithro/only-change-on-contents 
Only write file if contents will change.
 2019-09-02 14:42:22 -07:00
Tim 'mithro' Ansell 3ff6a18a45 Only write file if contents will change. 2019-09-02 14:26:41 -07:00
Florent Kermarrec a2938a7ae7 soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" 2019-08-31 18:34:08 +02:00
enjoy-digital 19d3acfc71
Merge pull request #251 from micro-FPGA/master 
atlantic JTAG UART working module
 2019-08-31 18:33:27 +02:00
Antti Lukats fb00ee85a2 Create atlantic.py 
atlantic JTAG uart for Intel FPGA's, working and tested on Intel C10LP EK
 2019-08-30 09:35:10 +02:00
Florent Kermarrec 41fe7cae0b core/spi: add minimal SPISlave 2019-08-29 09:46:20 +02:00
Florent Kermarrec b845755995 gen/fhdl/verilog: allow single element verilog inline attribute 2019-08-28 05:24:11 +02:00
Florent Kermarrec 5a7b4c3406 targets/nexys_video: generate clk100 2019-08-27 14:06:13 +02:00
Florent Kermarrec c179741cf3 software/bios: switch to standard CRLF 
Avoid setting terminal to "implicit CR in every LF" mode.
 2019-08-27 09:45:44 +02:00
Florent Kermarrec 0328ba7d6c tools/litex_term: add automatic check to see if we need to insert LF or not 2019-08-26 18:17:43 +02:00
Florent Kermarrec ffebd2076c bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) 2019-08-26 17:15:01 +02:00
Florent Kermarrec 4842bdcf08 tools/litex_term: add sdl_payload_length 2019-08-26 12:10:11 +02:00
Florent Kermarrec 3e30c64842 litex_setup: add litex-boards 2019-08-26 09:28:58 +02:00
enjoy-digital d79cd87dd6
Merge pull request #246 from gsomlo/gls-native-rv64 
software: use native toolchain for same host, target architectures
 2019-08-23 21:36:51 +02:00
Gabriel L. Somlo 6d844a038a software: use native toolchain for same host, target architectures 
LiteX rightfully assumes that most often the target software must
be cross-compiled from an x86 host platform. However, LiteX can be
also built on a 'linux-riscv64' platform (e.g. Fedora's riscv64
port), where the software for riscv64 targets should be compiled
using the native toolchain.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-08-23 09:04:55 -04:00
enjoy-digital d36f1fb7d2
Merge pull request #244 from atommann/master 
changing http to https
 2019-08-17 11:54:39 +02:00
atommann a45dbee54f changing http to https 2019-08-17 16:02:10 +08:00
Antti Lukats 92e5b4b2cd
Merge pull request #2 from enjoy-digital/master 
update with hyperram and other changes
 2019-08-16 14:36:59 +02:00
Florent Kermarrec 4990bf33c0 soc/core: simplify/cleanup HyperRAM core 
- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).

Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
 2019-08-16 14:04:58 +02:00
Antti Lukats f47e4978f2 libero enable enhanced constraints 
Libero 12.0 does not support any more classic constraint flow
 2019-08-16 10:31:53 +02:00
Antti Lukats d1502d4195 soc/cores: add initial simple hyperram core 2019-08-16 09:48:17 +02:00
Florent Kermarrec 6e6fe83af3 build/altera/quartus: add add_ip method to use Quartus QSYS files 
platform.add_ip("my_ip.qsys")
 2019-08-15 13:45:29 +02:00
Florent Kermarrec 2899928aba cpu_interface: add json csr map export, simplify csv csr map export using json 2019-08-15 09:27:33 +02:00
Florent Kermarrec 9d4b7cd515 bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) 2019-08-14 19:09:58 +02:00