591186279a
doc: add new logo
2019-06-08 00:45:30 +02:00
850b311d04
cpu/vexriscv: update submodule
2019-06-07 18:36:46 +02:00
755a2660ba
build/sim: allow configuring verilator optimization level
2019-06-07 12:28:20 +02:00
4b6ad8aa0d
build/sim: allow defining start/end cycles for tracing
2019-06-07 11:50:57 +02:00
ecb60f6e43
build/sim: use -O0 for verilator compilation
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In most of the case, execution speed is already fast enough with -O0 and
with complex design -O0 is a lost faster to compile than -O3. In the future
we could add a switch to choose which optimization we want.
2019-06-07 11:16:39 +02:00
c64129dc69
soc/integration/soc_core: list rocket as supported CPU
2019-06-07 11:14:36 +02:00
ca4e7811e9
software/bios: change prompt to "litex" in green.
2019-06-07 11:13:36 +02:00
8d0f008a3b
integration/soc_core: improve readibility (add separators/comments)
2019-06-05 23:43:16 +02:00
55ebcc00eb
test/test_targets: add de10lite
2019-06-05 20:03:19 +02:00
e545b15f66
Merge pull request #196 from msloniewski/de10lite_support
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De10lite support
2019-06-05 19:44:54 +02:00
77805a5e26
Merge pull request #195 from antmicro/extend_generated_headers
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Extend generated headers & csv
2019-06-05 19:20:15 +02:00
04ce479035
boards/targets: add target for de10lite platform
2019-06-05 18:57:59 +02:00
f2a740d51d
boards/platforms: add de10lite Terasic platform support
2019-06-05 18:57:59 +02:00
a826aacac0
build/altera: Add possibility to turn off generation of .rbf file
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For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.
2019-06-05 18:57:59 +02:00
93b61a65bf
integration/builder: generate flash_boot address to csv
2019-06-05 17:37:23 +02:00
d0b019b1f0
integration/builder: generate shadow_base address to mem.h and csv
2019-06-05 17:37:09 +02:00
cb2d4372e4
Merge pull request #193 from gsomlo/gls-memcpy-fix
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software/libbase: memcpy: simple, arch-width agnostic implementation
2019-06-04 21:49:18 +02:00
f88b85a31c
software/libbase: memcpy: simple, arch-width agnostic implementation
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Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.
Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-06-04 14:48:51 -04:00
42e9d09755
Merge pull request #192 from sutajiokousagi/pr_c99_types
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fix signed char type to be explicitly signed
2019-06-02 16:54:20 -07:00
ab0b2cac2e
fix signed char type to be explicitly signed
2019-06-03 06:01:13 +00:00
200d413def
update stdint.h to include c99 types
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needed for some third party libraries to compile
2019-06-02 22:27:12 +00:00
b0d35a49f2
Merge pull request #191 from sergachev/master
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Fix interrupt_name in soc_core/add_interrupt
2019-06-02 13:00:20 -07:00
db890736ea
fix csr_name in add_csr()
2019-06-02 20:56:02 +02:00
40cbe3a952
fix interrupt_name
2019-06-02 20:52:31 +02:00
b300c32103
test/test_targets: add de2_115, de1soc
2019-06-02 19:22:09 +02:00
220e2bdc6e
boards/platform/arty: add Arty A7-100 variant
2019-06-02 19:10:44 +02:00
8e6ecfb974
Merge pull request #189 from open-design/terasic-boards
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Add support for Terasic DE2-115 and Terasic DE1-SoC boards
2019-06-02 18:40:57 +02:00
9682189b40
Merge pull request #190 from sutajiokousagi/pr_c99_types
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update stdint.h to include c99 types
2019-06-02 08:15:52 -07:00
6cf1a814eb
boards: add Terasic DE2-115 initial support
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See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=1
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-02 11:33:10 +03:00
037259917a
boards: add Terasic DE1-SoC Board support
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See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-06-02 11:26:21 +03:00
a48858f828
Merge pull request #188 from gsomlo/gls-csr-cleanup
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Miscellaneous cleanup patches
2019-05-30 22:40:39 +02:00
273a3ea15d
soc/integration/cpu_interface: improve code legibility
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Factor out code appearing in both branches of an if/else.
2019-05-29 10:07:43 -04:00
08a811b1a5
soc/interconnect/gearbox: add msb_first/lsb_first order
2019-05-29 10:25:25 +02:00
675f78304e
boards/targets/arty: generate 25MHz ethernet clock with S7PLL
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Allow ethernet to work when sys_clk_freq != 100MHz
2019-05-28 09:55:06 +02:00
d7b00c8c4d
Merge pull request #187 from open-design/indent
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litex/boards/targets: don't use tab for indentation
2019-05-26 03:01:31 -07:00
26e6355fd6
litex/boards/targets: don't use tab for indentation
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Fix pep8 E101 "indentation contains mixed spaces and tab" error.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2019-05-26 12:00:03 +03:00
5109511259
soc/interconnect/axi: add round/robin arbitration between writes/reads
2019-05-25 10:02:31 +02:00
0fb6342f7b
travis: update RISC-V toolchain
2019-05-25 09:30:54 +02:00
961101d809
bios/irc: remove compilation workaround
2019-05-25 09:24:48 +02:00
cd543b290c
README: update RISC-V toolchain
2019-05-25 09:24:25 +02:00
7e837bf1d0
.gitmodules/rocket: switch to https://github.com/enjoy-digital/rocket-litex-verilog
2019-05-24 10:39:48 +02:00
712977a0cf
software/bios/isr.c: workaround compilation issue (need to be fixed)
2019-05-24 10:18:50 +02:00
28ba8b3201
soc/integration/soc_core: revert default mem_map (do specific RocketChip remapping for now)
2019-05-24 10:18:32 +02:00
cf369c437c
boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it)
2019-05-24 10:18:26 +02:00
aa640f2999
Merge pull request #186 from gsomlo/gls-rocket
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Experimental Support for 64-bit RocketChip
2019-05-24 10:15:02 +02:00
019fd94005
fixup: generated-verilog submodule for experimental Rocket support
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FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog ,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
2019-05-23 18:22:37 -04:00
1a530cf27d
soc/cores/cpu/rocket: Support for 64-bit RocketChip (experimental)
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Simulate a Rocket-based 64-bit LiteX SoC with the following command:
litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket
NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-05-23 15:59:51 -04:00
3de49118d9
Merge pull request #185 from gsomlo/gls-sim-sdram
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tools/litex_sim: restore functionality of '--with-sdram' option
2019-05-23 15:52:33 +02:00
e90caa8683
tools/litex_sim: restore functionality of '--with-sdram' option
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After LiteDRAM commit #50e1d478, an additional positional argument
('databits') is required by the PhySettings() constructor.
The value used here (32) will generate a 64MByte simulated SDRAM.
2019-05-23 08:56:50 -04:00
3a72688b28
Merge pull request #183 from xobs/usb-to-0x43
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Use 0x43/0xc3 for USB bridge magic packet
2019-05-21 07:19:15 +02:00
Florent Kermarrec
msloniewski
Mateusz Holenko
Gabriel L. Somlo
Tim Ansell
bunnie
Ilia Sergachev
Antony Pavlov