Sebastien Bourdeauducq
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decbd069fa
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sim: fix message debug formatting
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2012-03-08 15:27:35 +01:00 |
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Sebastien Bourdeauducq
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98e96b3952
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sim: make initialization cycle optional (selectable by function attribute)
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2012-03-06 19:43:59 +01:00 |
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Sebastien Bourdeauducq
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8160ced2e9
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sim: memory access
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2012-03-06 19:29:39 +01:00 |
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Sebastien Bourdeauducq
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db8f8bf2e3
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fhdl: register memory objects with namespace
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2012-03-06 18:33:44 +01:00 |
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Sebastien Bourdeauducq
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6f829c7afc
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sim: support for signed numbers
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2012-03-06 16:46:18 +01:00 |
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Sebastien Bourdeauducq
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90184b22d2
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fhdl/verilog: fix signed constant conversion
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2012-03-06 16:45:44 +01:00 |
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Sebastien Bourdeauducq
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0a23cadd38
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vpi: install target
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2012-03-06 15:51:09 +01:00 |
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Sebastien Bourdeauducq
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9da512dbf5
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sim: VCD generation
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2012-03-06 15:26:04 +01:00 |
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Sebastien Bourdeauducq
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22b3c11b93
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sim: clean startup/shutdown
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2012-03-06 15:00:02 +01:00 |
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Sebastien Bourdeauducq
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06de17b16c
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sim: remove temporary files and socket
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2012-03-06 14:20:26 +01:00 |
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Sebastien Bourdeauducq
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7230508e7c
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fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
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2012-03-06 14:18:22 +01:00 |
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Sebastien Bourdeauducq
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2c375e900f
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sim: remove default sockaddr
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2012-03-06 13:58:49 +01:00 |
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Sebastien Bourdeauducq
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8d16fde48c
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fhdl: add simulation functions in fragment
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2012-03-06 13:58:22 +01:00 |
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Sebastien Bourdeauducq
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aac9752558
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sim: basic functionality working
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2012-03-05 20:31:41 +01:00 |
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Sebastien Bourdeauducq
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c4c22c9ca0
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sim: signal writes working
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2012-03-05 15:40:21 +01:00 |
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Sebastien Bourdeauducq
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9bbec278c6
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sim: cleanups
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2012-03-04 22:56:56 +01:00 |
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Sebastien Bourdeauducq
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2cd71e4b5e
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sim: signal reads working
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2012-03-04 22:33:03 +01:00 |
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Sebastien Bourdeauducq
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c0b0161ec9
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sim: compile VPI module
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2012-03-04 21:27:02 +01:00 |
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Sebastien Bourdeauducq
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29859acc34
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sim: two way IPC working
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2012-03-04 19:17:03 +01:00 |
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Sebastien Bourdeauducq
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8586daf2dd
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sim: IPC module (lacks str/int encoding)
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2012-03-03 18:55:38 +01:00 |
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Sebastien Bourdeauducq
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7f307c54a9
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README: clarify license
|
2012-02-29 20:30:08 +01:00 |
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Sebastien Bourdeauducq
|
8d4a42887e
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ddrphy: working on hardware, simulation a bit messed up
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2012-02-24 15:44:51 +01:00 |
|
Sebastien Bourdeauducq
|
baba267db6
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ddrphy: request wrdata_en/rddata_en at the same time as the command
|
2012-02-24 15:14:58 +01:00 |
|
Sebastien Bourdeauducq
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17b2588321
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ddrphy: reads OK, write data coming out 1/2 cycle too late
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2012-02-24 15:05:52 +01:00 |
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Sebastien Bourdeauducq
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a363eb4a36
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ddrphy: partly working
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2012-02-24 13:54:10 +01:00 |
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Sebastien Bourdeauducq
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3179a27d14
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dfii: set data mask
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2012-02-23 22:00:51 +01:00 |
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Sebastien Bourdeauducq
|
92ac69bae3
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dfii: new design
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2012-02-23 21:21:07 +01:00 |
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Sebastien Bourdeauducq
|
b3ca952a39
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s6ddrphy: read path OK in simulation
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2012-02-21 17:38:40 +01:00 |
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Sebastien Bourdeauducq
|
b4e041ecf1
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s6ddrphy: write path OK in simulation
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2012-02-20 23:55:20 +01:00 |
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Sebastien Bourdeauducq
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ce51653381
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s6ddrphy: generate DQ/DQS/DM OE
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2012-02-20 16:13:56 +01:00 |
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Sebastien Bourdeauducq
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cbc3b7fa83
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s6ddrphy: DQ/DQS/DM SERDES
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2012-02-20 13:45:57 +01:00 |
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Sebastien Bourdeauducq
|
4c1e18a9b5
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s6ddrphy: clock, address and command
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2012-02-19 20:49:56 +01:00 |
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Sebastien Bourdeauducq
|
f35cd4a85b
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Prepare for new DDR PHY
|
2012-02-19 18:43:42 +01:00 |
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Sebastien Bourdeauducq
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1b8cb5b46c
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bus/dfi: fix multiphase naming
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2012-02-19 17:57:04 +01:00 |
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Sebastien Bourdeauducq
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1e4e092a55
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bios: fix function prototypes
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2012-02-18 21:06:35 +01:00 |
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Sebastien Bourdeauducq
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d8d4e81b6e
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bank/csrgen: fix RE generation
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2012-02-18 18:56:18 +01:00 |
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Sebastien Bourdeauducq
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026457a98c
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Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.
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2012-02-18 18:12:14 +01:00 |
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Sebastien Bourdeauducq
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55a265d967
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bank: add RE signal for registers made of fields
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2012-02-17 23:52:06 +01:00 |
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Sebastien Bourdeauducq
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92dfbb92dd
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bus: add interconnect statements function
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2012-02-17 23:51:32 +01:00 |
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Sebastien Bourdeauducq
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f995e8b92e
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fhdl: check we pass BV to signals
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2012-02-17 23:50:54 +01:00 |
|
Sebastien Bourdeauducq
|
5bc840b9c1
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DFI injector (untested)
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2012-02-17 23:50:10 +01:00 |
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Sebastien Bourdeauducq
|
c38de34a21
|
bios: DDR initialization skeleton
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2012-02-17 18:47:04 +01:00 |
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Sebastien Bourdeauducq
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e5927e265f
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bios: add flash target using m1nor
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2012-02-17 18:16:29 +01:00 |
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Sebastien Bourdeauducq
|
48ddbf0c85
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Add build Makefile and JTAG load script
|
2012-02-17 18:09:48 +01:00 |
|
Sebastien Bourdeauducq
|
c387ce7ce5
|
Map DDR PHY controls in CSR
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2012-02-17 17:34:59 +01:00 |
|
Sebastien Bourdeauducq
|
a1ad30faab
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fhdl/verilog: properly connect instance inouts
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2012-02-17 11:08:41 +01:00 |
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Sebastien Bourdeauducq
|
5d1dad583b
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Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
|
2012-02-17 11:04:44 +01:00 |
|
Sebastien Bourdeauducq
|
cdd58e023b
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s6ddrphy: use single-ended DQS
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2012-02-17 10:53:58 +01:00 |
|
Sebastien Bourdeauducq
|
cc5e4ae710
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clkfx: remove
|
2012-02-16 19:30:00 +01:00 |
|
Sebastien Bourdeauducq
|
204452b0d3
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m1crg: make clock feedback pin bidirectional
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2012-02-16 18:35:44 +01:00 |