5502cec3da
Add basic inttypes.h.
...
This is taken from glibc. Only PRI* definitions are imported;
functions are not.
2015-07-26 12:44:13 +03:00
eef1aa77ef
Mark abort() as __attribute__((noreturn)).
2015-07-26 12:43:22 +03:00
10f719a830
Add support for fprintf(stderr, ...).
2015-07-26 12:42:53 +03:00
f5cc6fb72d
Don't use clang for anything except or1k.
2015-07-26 10:00:58 +03:00
d03dabb460
common.mak: Pass -fexceptions to clang and clang++.
...
This results in generation of .eh_frame sections. These sections
can be discarded during final linking, or included if exception
handling is desired. For exception handling to work, all sources
must be built with -fexceptions.
2015-07-26 03:30:21 +03:00
69c2a705bf
common.mak: use clang/clang++ to compile C/C++ sources.
...
Note that -integrated-as is not active by default on OR1K,
so we're still shelling out to binutils to assemble.
It is not yet possible to build everything using -integrated-as.
2015-07-26 03:28:37 +03:00
0f47876d2e
common.mak: remove RANLIB.
...
`ranlib` is not necessary on any system we can possibly build for,
as it is superseded by `ar s` for the last ten years or so (at least).
Thus, change ar invocations to `ar crs`, also removing a `l` flag
that is ignored by binutils.
2015-07-26 03:20:23 +03:00
f500b906e6
common.mak: remove AS.
...
$(AS) was never used: $(assemble) invokes the C compiler instead.
In case of LLVM, this will allow us to consistently use the LLVM
internal assembler for both inline assembly in C and assembly
sources; so, avoid ever invoking binutils as explicitly.
2015-07-26 02:46:03 +03:00
84514cf8d5
uart: remove option to refill HW from uart_write
2015-07-19 23:41:38 +02:00
097248bce9
uart.c: rx overflow fix and tx simplification
...
* fixes the clearing of the rx ringbuffer on rx-overflow
* removes tx_level and tx_cts by restricting the ringbuffer
to at least one slot empty
* agnostic of the details of the tx irq: works for uarts that
generate tx interrupts on !tx-full or on tx-empty.
* only rx_produce and tx_consume need to be volatile
2015-07-19 23:37:00 +02:00
35250f5b11
bios: add romboot
...
When firmware is small enough, it can be interesting to run code from an embedded blockram memory (faster and not impacted by memory controller activity).
It can also be a fallback option in case boot from flash failed.
To use this, define ROM_BOOT_ADDRESS and initialize the blockram with the firmware data.
2015-07-14 18:01:44 +02:00
23541b5949
software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)
2015-07-04 21:04:23 +02:00
10eb07526d
bios: show memtest command in help
2015-07-02 17:20:06 +02:00
e913fca8a0
libcompiler-rt: add fixdfdi
2015-06-27 23:51:09 +02:00
351e654e9d
software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)
2015-06-23 09:01:34 +02:00
781869d6f9
software/libbase/system: fix flush_l2_cache
2015-06-19 09:00:14 +02:00
f44956bfca
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
2015-06-19 08:39:37 +02:00
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
a8b9c126cd
spiflash: now using 64k sectors
2015-05-27 18:44:14 +08:00
3f7e161867
spiflash: cleanup unnecessary parenthesis
2015-05-27 18:44:14 +08:00
438a0856c5
misoclib/cpu: merge git.py in identifier
2015-05-02 18:42:33 +02:00
e8c01ff4aa
do more test with last changes fix small issues
2015-05-02 16:22:38 +02:00
8aa3fb3eb7
com/uart: add tx and rx fifos.
...
Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.
2015-05-01 15:59:26 +02:00
1d9771f574
spiflash: use SoC defines, add write_to_flash function
2015-04-27 13:42:32 +08:00
0b1a2e1022
liteeth: do MII/GMII detection in gateware for gmii_mii phy
2015-04-26 18:08:07 +02:00
ae71bf2830
liteeth: fix and improve 10/100/1000Mbps speed auto detection
2015-04-26 14:54:53 +02:00
3710afe7fe
microudp.c: add #ifdef on ethmode (bios generation for gmii or mii was broken)
2015-04-12 20:59:50 +02:00
4abe8e1d9e
microudp: fix if (
2015-04-12 18:52:35 +02:00
515398634f
liteeth/phy/gmii_mii: add clock counter and use it in bios to select mode
2015-04-12 18:42:52 +02:00
c7361f1cdf
software/common.mak: fix alignment in quiet output
2015-04-03 17:43:29 +08:00
73d3b8487c
crt0-or1k: clean up indentation
2015-04-03 13:23:28 +08:00
63f14f3f30
libbase: implement flush_l2_cache for or1k
2015-04-02 16:47:03 +08:00
f4c35e358e
software/bios/sdram: small clean up
2015-03-27 18:24:19 +01:00
6245dd7b6f
software/bios/sdram: for now desactivate random on address test since it seems to trigger a L2 cache or LASMIcon bug on at least de0nano/minispartan6
...
Memtest sometimes reports 1 or 2 errors with de0nano/minispartan6 on this new test when used with LASMICON. Minicon seems fine. We will have to investigate on this issue.
2015-03-27 16:43:22 +01:00
f85a4f004b
software/bios/sdram: add random addressing to memtest
...
testing memories with linear access is not good enough. Adding random addressing allow us to detect more eventual issues on our L2 cache or SDRAM controller.
2015-03-27 15:49:16 +01:00
38d24b637e
software/bios/sdram: make seed_to_data static
2015-03-26 23:05:20 +01:00
e79a716425
software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter)
2015-03-26 22:16:31 +01:00
257706517e
software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
2015-03-26 00:01:42 +01:00
1fc24e66dc
sofware/memtest: use MAIN_RAM_SIZE from mem.h
2015-03-25 19:00:07 +01:00
94b62eff8b
libcompiler-rt: add ucmpdi2.o
2015-03-25 17:57:42 +01:00
69e9032d49
sofware/memtest: update bandwidth registers
2015-03-25 17:25:39 +01:00
6492ef1efa
linker-sdram.ld: sdram mem region is now called main_ram
2015-03-25 16:45:19 +01:00
9bc71f374a
rename sdram mapping to main_ram
2015-03-21 21:01:46 +01:00
b75e4b237d
software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion of the test zone.
...
we now need to add another random addressing test to avoid linear access on L2 cache
2015-03-21 20:29:15 +01:00
84b631c929
liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc
2015-03-19 14:52:02 +01:00
473997df26
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
8280acd3a7
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
2015-03-02 12:17:49 +01:00
0980becb56
sdram: improve memtest by adding 2 different writes/reads
...
doing only a write and read is not enough: if we reloaded a fpga with write that is not working after functional fpga, it would not trigger an error.
2015-03-02 10:52:22 +01:00
2c51adcd68
misoclib: better organization (create cores categories: cpu, mem, com, ...)
2015-02-28 09:40:44 +01:00
07b9cabd0d
gensoc: make it more generic (a SoC does not necessarily have a CPU)
2015-02-27 16:39:00 +01:00
whitequark
Sebastien Bourdeauducq
Robert Jordens
Florent Kermarrec
Yann Sionneau