79e5f24a65
Workaround for zero-delay loop simulation problem with Icarus Verilog. TODO: clarify and revert this commit.
2012-11-28 22:49:22 +01:00
0620e75cb8
sram: do not use MemoryPort
2012-11-26 19:32:56 +01:00
0c29775a8f
tb/asmicon/asmicon_wb: more complete testing by default
2012-11-26 18:19:41 +01:00
5ae1b2644e
tb/asmicon: new initiator API
2012-11-17 19:43:30 +01:00
a0ff666628
lm32: replace $clog2 with macro
...
Unfortunately, XST does not support $clog2 with the localparam keyword
(the parameter keyword works just fine). Define a macro which replaces the
call with a constant function.
This commit can be reverted if the bug in XST is fixed.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:30:16 +01:00
d15d982904
lm32: split lm32_include.v
2012-11-14 14:25:15 +01:00
2ae17af75b
lm32: fix documentation style
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Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:09:21 +01:00
4bee685c54
lm32: remove unneeded parameter in lm32_dp_ram
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addr_depth can be computed by addr_width.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:41 +01:00
10495e72d0
lm32: rename mem array in lm32_dp_ram
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Be compatible with original proprietary DP RAM instantiation. This is
needed for simulation, where r0 is initialized to zero in lm32_cpu.v.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:08:06 +01:00
47baad4fe1
lm32: replace clogb2 by builtin $clog2
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This function is fixed in ISE since version 14.1 (see AR #44586 ). If the
builtin function is used, the design can be simulated with Icarus Verilog.
Signed-off-by: Michael Walle <michael@walle.cc>
2012-11-14 14:07:28 +01:00
ced98d7bee
framebuffer: use new SingleGenerator
2012-10-09 21:11:26 +02:00
dd6eacba62
Remove uses of the RE signal on field registers
2012-10-09 19:08:37 +02:00
c86dd3cbef
Define clock domains instead of passing extra clocks as regular signals
2012-09-11 00:21:07 +02:00
5931c5eb59
Basic support for new clock domain and instance API
2012-09-10 23:47:06 +02:00
42d5e850fe
framebuffer: disable debugger by default
2012-08-05 01:11:37 +02:00
5ef8d5f534
bios/dataflow: use freeze register
2012-08-04 23:39:29 +02:00
a5d6ced181
asmicon: fix and simplify refresh grant logic
2012-08-04 22:59:21 +02:00
ea4c214790
asmicon/bankmachine: respect SDRAM write-to-precharge specification
2012-08-04 22:49:43 +02:00
1451cad710
asmicon/multiplexer: correct read-to-write delay to prevent conflicts on the tag bus
2012-08-04 17:38:42 +02:00
274a00217e
bios: asmiprobe command
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Because with reordering architectures come order-dependent intermittent bugs.
2012-08-04 16:32:15 +02:00
855eec776d
Add ASMIprobe core
2012-08-04 16:31:24 +02:00
6807dba8bc
asmicon/bankmachine/selector: fix round-robin CE
2012-08-03 22:33:52 +02:00
df2b653c67
asmicon/bankmachine: do not insert buffer when using _SimpleSelector
2012-08-03 22:11:16 +02:00
6078a4e6d0
tb/selector: use _SimpleSelector
2012-08-03 22:10:04 +02:00
5bbdab1fd6
tb/asmicon: concurrent reads and writes
2012-08-03 22:09:23 +02:00
bf8f387324
asmicon: bring full_selector param to top-level
2012-08-03 21:23:54 +02:00
eb751f6e80
bios: add command to print df debug info
2012-08-03 18:51:39 +02:00
0642f0ca94
framebuffer: support df debugger
2012-08-03 18:51:18 +02:00
6073f68b69
asmicon: simple selector option
2012-07-13 19:25:38 +02:00
768a3a826a
x.bv.width -> len(x)
2012-07-13 18:33:03 +02:00
809cd99205
asmicon: remove uses of multimux
2012-07-13 18:05:26 +02:00
99b889a551
framebuffer: clean shutdown
2012-07-12 20:13:31 +02:00
b7aec21a47
top: use two slots for the framebuffer ASMI port
2012-07-12 19:40:49 +02:00
58d1e8a541
framebuffer: use ASMI reader factory
2012-07-12 18:56:17 +02:00
73a58977e4
framebuffer: print rgb in simulation
2012-07-07 11:34:22 +02:00
da478d044a
tb/framebuffer: remove vcd
2012-07-07 11:30:43 +02:00
99bb705407
framebuffer: fix FIFO read clocking
2012-07-07 11:30:27 +02:00
2dfdc8f3c5
Revert "framebuffer: switch to real DMA"
...
This reverts commit 3add96212b
2012-07-07 10:58:13 +02:00
3add96212b
framebuffer: switch to real DMA
2012-07-07 00:23:56 +02:00
ce82f188d0
framebuffer: fix deadlock
2012-07-07 00:12:34 +02:00
de28760913
tb/framebuffer: compute parameters
2012-07-07 00:11:58 +02:00
2b85624924
framebuffer: make simulation easier
2012-07-03 19:04:44 +02:00
210e473b5d
framebuffer: fix computation of alignment bits
2012-07-03 18:14:39 +02:00
59289cfa3b
framebuffer: indentation
2012-07-01 22:30:07 +02:00
e2463da787
framebuffer: fake DMA for testing (WIP)
2012-07-01 21:46:11 +02:00
fc458a51c9
framebuffer/vtg: fix dataflow control (inc. WA for Migen bug - FIXME)
2012-07-01 21:45:52 +02:00
7bf5461ac0
framebuffer: fix pixel split
2012-07-01 21:44:33 +02:00
0a29b74cce
framebuffer: fix sync generation
2012-07-01 18:43:39 +02:00
6776e2275c
Work around imbecilic timing constraints system
2012-07-01 18:14:16 +02:00
8ba3118a83
framebuffer: register output of FIFO
2012-07-01 18:13:49 +02:00
Sebastien Bourdeauducq
Michael Walle