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214 commits

Author SHA1 Message Date
Florent Kermarrec
4368d5a9ed test/test_led: Comment out TestWS1812 test since seems broken, will need to be investigated/fixed. 2024-10-28 21:51:42 +01:00
Andelf
8c7e510473 Fixes #2103: calculate memory depth for WS2812 
See-also: https://github.com/m-labs/migen/pull/295
 2024-10-25 11:48:57 +08:00
Florent Kermarrec
c554752e8a soc/cores/hyperbus: Add automatic read burst detection. 2024-08-30 11:53:14 +02:00
Florent Kermarrec
fac80c3a51 soc/cores/hyperbus: Full rewrite of HyperRAM core. 
Rewriting the HyperRAM core to improve its design and functionality. The
old core grew complex over time without a clear structure. This new version
offers:
- IO registers on all signals for better performance.
- Flexible clocking options.
- Simplified architecture.
- Easier to extend with new features.

This rewrite provides a base for future development.
 2024-08-29 12:54:09 +02:00
Florent Kermarrec
a88cee70c8 test/test_hyperbus: Update. 2024-08-21 19:22:56 +02:00
Florent Kermarrec
5587f5954d test/test_hyperbus: Add 2:1 test. 2024-08-21 15:00:11 +02:00
Florent Kermarrec
50f0a1057c soc/cores/hyperbus: Do some tests with sys_2x, seems working. 2024-08-21 10:57:36 +02:00
Florent Kermarrec
60f83b71fa soc/cores/hyperbus: Avoid dq_oe condition to generate dq_o (was only useful for sim but now avoided). 2024-08-20 21:54:15 +02:00
Florent Kermarrec
76cf004913 test/test_hyperbus: Update. 2024-08-20 15:17:36 +02:00
Andrew Dennison
67e6614eb2 test_i2c: whitespace cleanups 2024-07-20 15:45:44 +10:00
Radek Pesina
643f3f9a93 test_i2c: add more commands 2024-07-20 15:45:44 +10:00
Andrew Dennison
f99658200e soc/cores/i2c: rewrite state machine 
* Fix READ: was reading too many bits
* CLeaner transitions between states: ACK=>IDLE with scl=0. Other to IDLE with scl=1
* Now cleanly supports RESTART
* conceptual support for compound commands - not exposed yet
* fix tests: now appears to be I2C compliant
 2024-07-20 15:45:44 +10:00
Andrew Dennison
13811aeacb test_i2c: update to use improved _MockTristate 
* test now checks the actual i2c bus state, not the I2CMaster output
* refactor to eliminate some copy/paste
* tests now work again with this change: 'only change SDA when SCL is stable'
 2024-07-20 15:45:44 +10:00
Andrew Dennison
b779933a5f test_i2c: improve and document _MockTristate* 
Added i_mock for simulated external device:
    * when _oe = 0 _i = _i_mock
    * when _oe = 1 _i = _o
 2024-07-20 15:45:44 +10:00
Andrew Dennison
64ccd6df1c test_i2c: allow unit test to run directly 2024-07-20 15:45:44 +10:00
Andrew Dennison
90128756f9 test_i2c: test reading config 2024-07-20 15:45:44 +10:00
Andrew Dennison
4ddab34714 test_i2c: generate i2c.vcd 2024-07-20 15:45:44 +10:00
Andrew Dennison
a079da922a soc/cores: adapt misoc i2c to litex 
Also add misoc license information.
 2024-07-20 15:45:44 +10:00
Andrew Dennison
9dc3eefb7d soc/cores/i2c: import from misoc 
* unmodified - integration to follow
* from: https://github.com/m-labs/misoc @ 26f039f Dec 2022
 2024-07-20 15:45:44 +10:00
Jiaxun Yang
af3d2a29fc
csr_bus: Honour re signal from the upstream bus 
Currently CSR bus assumed that ~we means reading, that created
a problem that when for a CSR if reading has side effects and adr
parked unintentionally at that CSR, the reading side effect will be
triggered.

For SoCs, this happened when upstream bus issued a write transaction
with wishbone.sel, then on CSR bus it will be translated
as adr = addr, we = 0, which will be interpreted as a read to such
address, and trigger undesired side effect for such CSR.

Such upstream transaction will be generated by our bus width converter.

Given that we signal already presents in CSR Interface, the easiest way
to handle such situation is to generate re signal at bus bridges and
propagate it all the way down to the Interface.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
 2024-06-23 19:35:19 +01:00
Florent Kermarrec
8eaa53ae9a test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated). 2024-05-14 12:53:09 +02:00
Florent Kermarrec
d324c0e150 test/test_cpu: Disable Microwatt that seems to be broken. 2024-04-20 08:51:10 +02:00
Florent Kermarrec
3978af9c39 test/test_hyperbus: Update. 2024-04-16 11:12:30 +02:00
enjoy-digital
576ab24b6c
Merge pull request #1926 from enjoy-digital/hyperbus_variable_latency 
HyperRAM: Add variable latency and configuration support.
 2024-04-15 17:39:04 +02:00
Florent Kermarrec
6216bd4e99 cores/hyperbus: Add latency_mode parameter and test different latencies/modes in simulation. 2024-04-15 10:32:13 +02:00
Florent Kermarrec
b192103822 cores/hyperbus: Fix bytes order on register writes. 2024-04-12 16:06:26 +02:00
Florent Kermarrec
fb519ac260 test/test_hyperbus: Add test_hyperram_reg_write. 2024-04-12 15:21:57 +02:00
Andrew Dennison
5ae098ebc6 test/spi_mmap: be less verbose 
don't print miso/mosi changes with -v
 2024-04-05 12:35:47 +11:00
Andrew Dennison
c2da8de7b0 test_spi_mmap: tests for slot 0&1 2024-04-05 12:35:47 +11:00
Andrew Dennison
416f1b4281 cores/spi_mmap: add slot post transfer cs_wait 
Also remove unused slot_status - maintains CSR alignment now that
slot_control is 64 bit (two 32bit registers).
 2024-04-05 12:35:47 +11:00
Andrew Dennison
f3b287addd cores/spi_mmap: add 24-bit slot length 2024-04-05 12:31:39 +11:00
Andrew Dennison
a9c007d8d7 test/spi_mmap: add some SPIMMAP tests 
Some pass and some fail demonstrating issues observed in driver
development.

run unittest with -v to see more test details.

Ran 9 tests in 4.161s

FAILED (failures=4)
 2024-04-05 12:31:39 +11:00
Andrew Dennison
4bc47c959f test/spi_mmap: lint and autoformat with Ruff 2024-04-05 12:31:39 +11:00
Florent Kermarrec
722b6da9fb test/test_wishbone: Improve origin_region_remap_test to test more complex remapping. 2024-02-28 19:11:55 +01:00
Florent Kermarrec
129446dea2 test/test_wishbone: Run all Remapper tests in byte and word modes and simplify. 2024-02-21 11:20:01 +01:00
Florent Kermarrec
6213fd2151 test/test_wishbone: Add Remapper unit-test for word addressing mode. 2024-02-21 11:05:35 +01:00
Florent Kermarrec
d1e73889f9 test/test_wishbone: Add wishbone.Remapper basic tests. 2024-02-20 16:51:32 +01:00
enjoy-digital
ff271b0b5f
Merge pull request #1816 from motec-research/test_csr_status_issue 
test_csr: test cases to demonstrate a CSRStatus() issue
 2023-10-27 12:52:25 +02:00
Florent Kermarrec
002aad7a43 soc/test: Make data_width/address_width/addressing explicit on Wishbone.Interface calls. 2023-10-27 10:55:13 +02:00
Andrew Dennison
203726bc03 test_csr: test cases for issue 
'status' reads as 0 in simulation when CSRStatus has fields.
 2023-10-27 13:05:51 +11:00
Florent Kermarrec
577674bff2 test: Add minimal test_spi_mmap with simulation of SPIMaster. 2023-08-04 17:51:22 +02:00
enjoy-digital
33fbf558a2
Merge branch 'master' into avalon-burst-test 2023-05-10 11:12:30 +02:00
Hans Baier
71a0e398a7 Avalon2Wishbone test: assert readdatavalid on bursts 2023-05-10 04:05:16 +07:00
Hans Baier
f00eb4e112 AvalonMM2Wishbone: use same addressing on avalon and wishbone, leave address translation to the user 2023-05-09 15:26:27 +07:00
Florent Kermarrec
8e1a3880d3 interconnect/avalon: Switch to directory/python package and split mm/st. 
Similarly to what is done for AXI and will avoid too complex/large files.
 2023-05-08 09:25:16 +02:00
Hans Baier
c5c7e86cca
WIP AvalonMM interface and Avalon to Wishbone Bridge (#1674) 
Add initial AvalonMM interface and AvalonMM2Wishbone.
 2023-05-08 08:42:10 +02:00
Joel Stanley
3922359ba1 test: Reinstate microwatt and neorv32 
They appear to be passing CI again.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2023-02-27 17:46:41 +10:30
Florent Kermarrec
5c922320a0 test/test_cpu: Disable NeoRV32 in CI (Seems to be broken with Verilator update). 2023-01-23 08:44:57 +01:00
Florent Kermarrec
461b48fbaa test/test_cpu: Disable microwatt test for now since seems broken (GHDL issue). 
Will need to be investigated:
https://github.com/enjoy-digital/litex/actions/runs/3900056883/jobs/6662146988

Command line:
ghdl --synth --out=verilog --std=08 --no-formal /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/wishbone_types.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/utils.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/common.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/nonrandom.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fetch1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cache_ram.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/plrufn.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/dcache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/icache.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/insn_helpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/predecode.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/control.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/decode2.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/register_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/crhelpers.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/cr_file.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/ppc_fx_insns.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/logical.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/rotator.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/countbits.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/execute1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/loadstore1.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/divider.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/fpu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/pmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/writeback.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/mmu.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core_debug.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/core.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply.vhdl /home/runner/work/litex/pythondata-cpu-microwatt/pythondata_cpu_microwatt/vhdl/multiply-32s.vhdl /home/runner/work/litex/litex/litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl -e microwatt_wrapper
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : elab-vhdl_annotations.adb:1401
Call stack traceback locations:
0x7fc79b8b0542 0x5631cf7cd3d0 0x5631cf7c8bf1 0x5631cf7c9219 0x5631cf7c93d2 0x5631cf7c977f 0x5631cf7ca0d3 0x5631cf7ca21a 0x5631cf7c9c41 0x5631cf7cbc0c 0x5631cf889270 0x5631cf97faf6 0x5631cf857fb0 0x5631cf988b5a 0x5631cf6d43d7 0x7fc79b432d8e 0x7fc79b432e3e 0x5631cf6d2f83 0xfffffffffffffffe
 2023-01-12 11:43:17 +01:00
Florent Kermarrec
497eac09a0 test/test_axi/test_axi_width_converter: Rename and cleanup. 2022-12-08 21:39:08 +01:00