7eaa5f7372
targets/kc705: avoid ddrphy/ethphy address conflict
2014-11-20 17:11:57 -08:00
603c2641bb
new Ethernet MAC
2014-11-20 16:47:22 -08:00
2b7779d3b6
link: wip bfm
2014-11-12 18:20:34 +01:00
b423c1df4b
link: prepare simulation
2014-11-11 18:47:34 +01:00
64ed34b35a
clean up
2014-11-11 16:15:28 +01:00
705819f885
use new EndpointDescription
2014-11-11 14:54:54 +01:00
67aaf09b53
link: SATALinkLayer skeleton
2014-11-11 12:29:37 +01:00
294855e292
phy: use primitives dict and use only sata.std
2014-11-11 10:19:24 +01:00
30964db4a1
phy: send 2 ALIGN primitives every 256 DWORDs
2014-11-11 09:57:43 +01:00
f4d6ac8393
README: remove compiler-rt download instructions
2014-11-06 18:02:02 -08:00
09773df186
software: make compiler-rt a submodule
2014-11-06 18:00:28 -08:00
353e7fc13b
link: add SATALinkLayer skeleton (wip)
2014-11-04 22:55:31 +01:00
8f6354f2a3
link: improve crc_tb/ preamble_tb and increase length
2014-11-04 17:06:03 +01:00
c810009387
link: add Scrambler and testbench
2014-11-04 16:40:21 +01:00
8062298668
link: add CRC and testbench
2014-11-04 10:33:11 +01:00
449daedab7
sata/link: add crc and scrambler C models from SATA specification
2014-11-03 18:11:14 +01:00
47b5ff5e33
move code and create a directory for each layer
2014-11-03 17:38:12 +01:00
8c5c32751e
add input pipe stage option
2014-10-28 20:53:26 +01:00
25e0ccae9a
remove DRP ports (won't be used for now)
2014-10-28 11:33:15 +01:00
3f7406a937
various fixes and simplifications, SATA1 & SATA2 OK
2014-10-28 02:15:19 +01:00
e2cbb3a048
platforms: merge but keep support for iMPACT for now (xc3sprog need to be tested on Windows)
2014-10-24 12:32:08 +02:00
8e4b89849c
use new direct access on endpoints
2014-10-20 23:13:37 +08:00
34ed315a48
remove trailing whitespaces
2014-10-17 17:14:40 +08:00
d860813dec
use new direct access on endpoints
2014-10-16 17:57:30 +02:00
bbfce2b707
ctrl: drive txcomwake and not gtx.txcomwake in K7SATAPHYDeviceCtrl
2014-10-16 10:38:26 +02:00
9649b1497c
uart2wishbone: fix missing payload.d
2014-10-16 09:37:43 +02:00
2319ee0ab7
uart2wishbone: always use payload.d and not .d
2014-10-15 12:13:22 +02:00
027ddc65ca
fill __init__.py to simplify imports
2014-10-10 17:24:36 +02:00
bf95ea6c1c
mila: simplify usage
2014-10-10 16:17:12 +02:00
d0c9838dca
uart2wishbone: share UARTRX and UARTTX with MiSoC
2014-10-10 15:15:58 +02:00
20528c622a
mor1kx: sync
2014-10-10 15:38:05 +08:00
e53fb88b85
uart: minor cleanup and fix
2014-10-10 15:33:27 +08:00
5e5f436aa6
uart: split it and use dataflow
...
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
2014-10-10 15:24:47 +08:00
ba30a01830
mila: fixes when used without RLE
2014-10-06 12:30:06 +02:00
f72f11f7b4
mila: add clk_domain support
...
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.
future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
7043e6a5f3
mila: simplify export
2014-10-01 10:06:59 +02:00
b284819d18
revert simulation design and add wave
2014-09-30 11:10:15 +02:00
110580eb2e
add .payload. to Sink and Source to be compatible with upstream Migen
2014-09-30 11:03:36 +02:00
f5001751d0
instanciate GTXE2_COMMON (seems recommended in AR43339)
2014-09-30 10:57:52 +02:00
cf084fd079
test to visualize OOB with Miscope
2014-09-30 10:17:15 +02:00
bc5b23b808
use SGMII clk (125MHz) and SFP for test on KC705
2014-09-30 09:07:15 +02:00
d47917e480
simplify and clean up
2014-09-30 00:50:03 +02:00
0791b9e2e4
sim working
2014-09-29 17:12:02 +02:00
b47153fbfa
fix alignment (still some transmissions errors --> need to check clocks and resets)
2014-09-29 15:37:35 +02:00
ed752758b0
fix and simplify ctrl fsms, OOB OK, align KO
2014-09-27 17:45:46 +02:00
2f769e4e4e
gtx: add resynchronization on control signals
2014-09-27 17:26:05 +02:00
f23c5aa724
mmcm: configure default divider with default_speed
2014-09-27 16:22:40 +02:00
45f7f8aff5
add tx_reset_fsm and rx_reset_fsm
2014-09-27 16:10:39 +02:00
c27f24c4c0
reorganize code
...
- use sys_clk of 166.66MHz and using it instead of sata clk.
- rename clocking to CRG since it also handles resets.
- create datapath and move code from gtx.
2014-09-27 15:34:28 +02:00
879478a6e4
clocking: clean up and add comments
2014-09-27 13:33:43 +02:00
Sebastien Bourdeauducq
Florent Kermarec