51c9f84ef0
create LiteEthIPStack skeleton
2015-01-29 01:03:47 +01:00
5b37068393
make packetizer/depacketizer generic and use it for all layers
2015-01-29 00:25:55 +01:00
dc5e1aa1ad
mac: add packetizer/depacketizer (untested)
2015-01-29 00:02:50 +01:00
6249209f94
mac: use eth_phy_description inside mac
2015-01-28 22:49:49 +01:00
98b82348e7
common: add mac/arp/ip/udp header descriptions
2015-01-28 22:43:58 +01:00
ddf0579644
test: mac_wishbone_tb OK
2015-01-28 21:54:09 +01:00
44113d754f
mac: change default interface (core)
2015-01-28 20:55:18 +01:00
fb00202427
test: mac_core_tb OK
2015-01-28 20:44:41 +01:00
33edf11ec9
test: add mac simulation skeleton
2015-01-28 19:07:59 +01:00
8a42d74904
setup.py: fix
2015-01-28 13:16:29 +01:00
e42fdb4232
test integration in MiSoC (fixes/cleanup)
2015-01-28 11:56:28 +01:00
09537523a6
test: add PHY model skeleton
2015-01-28 10:25:33 +01:00
8a2b65f21d
continue code refactoring
2015-01-28 09:28:33 +01:00
4cd73fc9da
change name to LiteEth (LiteEthernet is too long...)
2015-01-28 01:36:38 +01:00
8477974ef1
start code adaptation
2015-01-28 00:51:31 +01:00
0826811047
etherbone: import core from Robert Jordens
2015-01-28 00:10:26 +01:00
46c4841d68
mac: import files from MiSoC
2015-01-27 23:59:06 +01:00
a160b04d2f
init repo
2015-01-27 23:50:52 +01:00
9bb7e6d0ab
ethmac: improve testbenchs
2014-12-21 17:37:25 +08:00
ceb675c3f1
fix cf92821 merge issue
2014-12-19 21:49:49 +08:00
aac34f011f
gensoc: support user-defined CSR regions
2014-11-30 22:29:26 +08:00
8ae3a00a94
gensoc: simplify WB address decoding
2014-11-30 22:05:51 +08:00
4189440eef
minicon: small simplifications
2014-11-28 08:28:39 +08:00
edb1622668
spiflash: BB write support
2014-11-27 23:10:39 +08:00
bab6bb7c4a
gensoc: fix align
2014-11-27 23:05:36 +08:00
2cd80990e4
minicon: fix use of phy phases
2014-11-27 22:13:17 +08:00
8418ccafdc
minicon: remove unused signals and fix indent
2014-11-27 22:12:05 +08:00
cf92821fcf
Refactor directory hierarchy of sdram phys and controllers
2014-11-27 22:09:10 +08:00
f33b285af1
Minicon: small SDRAM controller
2014-11-27 22:09:03 +08:00
5202f89db1
ethmac/last_be: remove fake signal (fixed in Migen)
2014-11-21 14:48:17 -08:00
b7028848b2
ethmac: use new EndpointDescription API
2014-11-20 22:32:32 -08:00
33530e0921
ethmac: style/renaming
2014-11-20 18:01:48 -08:00
7eaa5f7372
targets/kc705: avoid ddrphy/ethphy address conflict
2014-11-20 17:11:57 -08:00
603c2641bb
new Ethernet MAC
2014-11-20 16:47:22 -08:00
f4d6ac8393
README: remove compiler-rt download instructions
2014-11-06 18:02:02 -08:00
09773df186
software: make compiler-rt a submodule
2014-11-06 18:00:28 -08:00
8e4b89849c
use new direct access on endpoints
2014-10-20 23:13:37 +08:00
34ed315a48
remove trailing whitespaces
2014-10-17 17:14:40 +08:00
20528c622a
mor1kx: sync
2014-10-10 15:38:05 +08:00
e53fb88b85
uart: minor cleanup and fix
2014-10-10 15:33:27 +08:00
5e5f436aa6
uart: split it and use dataflow
...
This make the code easier to understand and allow the reuse of UARTRX & UARTTX
on designs without CPU (e.g miscope).
2014-10-10 15:24:47 +08:00
c1fc0b9c97
update README with new Kintex-7 support
2014-09-26 10:36:29 +08:00
13fb9282db
targets: add simple design (vendor agnostic and usable on all platforms with UART pins).
...
Designing a SoC with Migen is easy, but we have to provide a very simple design that can
be used on all boards with only 1 clock and 2 UARTs pins defined. This will encourage the
newcomer to invest time in Migen/MiSoC and see its real potential.
2014-09-26 10:35:15 +08:00
410f250d2a
software: remove setjmp
2014-09-23 21:57:05 +08:00
14d53526be
libbase: use __builtin_setjmp and __builtin_longjmp
2014-09-21 17:43:17 +08:00
503a2f00b5
mor1kx: sync
2014-09-12 16:00:32 +08:00
c0c17030fd
spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters
2014-09-04 15:23:39 +08:00
36434b62f0
sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE
2014-09-03 15:02:38 +08:00
2388bfabc3
bios: support DDR3 write leveling and read calibration. This makes the full DDR3 SODIMM work on the KC705.
2014-09-03 14:25:26 +08:00
a7b4550e59
sdramphy/initsequence: cleanup and expose DDR3 MR1 value
2014-09-03 14:21:30 +08:00
Florent Kermarrec
Sebastien Bourdeauducq
Yann Sionneau