Sebastien Bourdeauducq
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7093939309
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corelogic/roundrobin: fix request width (again)
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2012-11-29 23:47:51 +01:00 |
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Sebastien Bourdeauducq
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31c722f993
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corelogic/roundrobin: fix request width
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2012-11-29 23:47:08 +01:00 |
|
Sebastien Bourdeauducq
|
70e97e0456
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Fix various errors from new bitwidth/signedness system conversion
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2012-11-29 23:36:55 +01:00 |
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Sebastien Bourdeauducq
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261166d92b
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fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
See http://jandecaluwe.com/hdldesign/counting.html
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2012-11-29 22:59:54 +01:00 |
|
Sebastien Bourdeauducq
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55d143a454
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fhdl/structure: add unary minus
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2012-11-29 22:52:57 +01:00 |
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Sebastien Bourdeauducq
|
d8e478efee
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Replace Signal(bits_for(... with Signal(max=...
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2012-11-29 21:53:36 +01:00 |
|
Sebastien Bourdeauducq
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50ed73c937
|
New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
|
Sebastien Bourdeauducq
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6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
|
Sebastien Bourdeauducq
|
070652cc39
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pytholite/reg: use source id in dictionary
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2012-11-29 00:09:35 +01:00 |
|
Sebastien Bourdeauducq
|
fee22a4631
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Remove Constant
|
2012-11-28 23:18:43 +01:00 |
|
Sebastien Bourdeauducq
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59831e0485
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fhdl/structure: improved bits_for function
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2012-11-28 18:39:44 +01:00 |
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Sebastien Bourdeauducq
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11b1e53224
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visit/NodeTransformer: copy most nodes
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2012-11-28 17:50:55 +01:00 |
|
Sebastien Bourdeauducq
|
a2bcbfdf8f
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fhdl/tools: use NodeTransformer to lower arrays
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2012-11-28 17:46:15 +01:00 |
|
Sebastien Bourdeauducq
|
3bc15024ac
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fhdl/tools: use NodeVisitor
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2012-11-26 21:40:23 +01:00 |
|
Sebastien Bourdeauducq
|
e3a983d731
|
Remove unroll
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2012-11-26 20:07:48 +01:00 |
|
Sebastien Bourdeauducq
|
1460f069f6
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fhdl/structure: remove deprecated MemoryPort
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2012-11-26 19:36:43 +01:00 |
|
Sebastien Bourdeauducq
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5183774ec8
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bus/wishbone2asmi: do not use MemoryPort
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2012-11-26 19:14:59 +01:00 |
|
Sebastien Bourdeauducq
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fc85ca53ad
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actorlib/spi: do not use MemoryPort
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2012-11-26 18:27:59 +01:00 |
|
Sebastien Bourdeauducq
|
dac0d11e52
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actorlib/sim: Dumper
|
2012-11-24 00:00:07 +01:00 |
|
Sebastien Bourdeauducq
|
27d87c9412
|
fhdl/structure: disable we_granularity when larger than width
|
2012-11-23 23:08:12 +01:00 |
|
Sebastien Bourdeauducq
|
d2c61e6a90
|
sim/generic/multiread: do not return spurious items
|
2012-11-23 23:07:25 +01:00 |
|
Sebastien Bourdeauducq
|
74721b206f
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pytholite: fix import of _Slice
|
2012-11-23 21:20:18 +01:00 |
|
Sebastien Bourdeauducq
|
95122bb778
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pytholite/io: support memory
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2012-11-23 20:36:09 +01:00 |
|
Sebastien Bourdeauducq
|
f42683b71e
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fhdl/structure/Memory: fix we width
|
2012-11-23 19:21:52 +01:00 |
|
Sebastien Bourdeauducq
|
0f6215a13a
|
fhdl/structure: add Memory.get_port API
|
2012-11-23 19:17:49 +01:00 |
|
Sebastien Bourdeauducq
|
9d3e218863
|
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.
|
2012-11-23 18:38:03 +01:00 |
|
Sebastien Bourdeauducq
|
3971600917
|
fhdl/structure: use sets for memories and instance collections
|
2012-11-23 17:20:08 +01:00 |
|
Sebastien Bourdeauducq
|
f3efd74dfd
|
uio: support memories
|
2012-11-23 16:23:24 +01:00 |
|
Sebastien Bourdeauducq
|
ab31b4d99c
|
bus: memory initiator
|
2012-11-23 16:22:50 +01:00 |
|
Sebastien Bourdeauducq
|
0b7dd7bdce
|
pytholite/io: fix Wishbone writes + support sel attribute
|
2012-11-23 13:40:46 +01:00 |
|
Sebastien Bourdeauducq
|
4c216d8f11
|
pytholite/io: support Wishbone reads
|
2012-11-23 13:09:55 +01:00 |
|
Sebastien Bourdeauducq
|
0b24a2ff36
|
pytholite/io: support Wishbone writes
|
2012-11-23 12:41:50 +01:00 |
|
Sebastien Bourdeauducq
|
f098c5c695
|
pytholite/compiler: pass keyword arguments to gen_io
|
2012-11-23 12:40:57 +01:00 |
|
Sebastien Bourdeauducq
|
51e2e6ecd0
|
fhdl/verilog: remove empty cases
|
2012-11-18 16:32:51 +01:00 |
|
Sebastien Bourdeauducq
|
89643bc434
|
sim/ipc/Message: convert values
|
2012-11-17 23:19:40 +01:00 |
|
Sebastien Bourdeauducq
|
e92af9de59
|
pytholite/transel: use python3-compatible comparison methods
|
2012-11-17 23:16:07 +01:00 |
|
Sebastien Bourdeauducq
|
b6b4c5d70e
|
uio/ioo: fix UnifiedIOSimulation
|
2012-11-17 22:25:42 +01:00 |
|
Sebastien Bourdeauducq
|
1cabcb3c3f
|
uio: support generator trampolining in simulation
|
2012-11-17 19:59:22 +01:00 |
|
Sebastien Bourdeauducq
|
be68ecfc72
|
uio: add simulation I/O object
|
2012-11-17 19:55:33 +01:00 |
|
Sebastien Bourdeauducq
|
7add4c6f3c
|
uio: unified I/O object
|
2012-11-17 19:54:50 +01:00 |
|
Sebastien Bourdeauducq
|
d10df1a8ab
|
actorlib/sim: swap TokenExchanger parameters
|
2012-11-17 19:46:28 +01:00 |
|
Sebastien Bourdeauducq
|
d4baac6c0f
|
bus/csr: allow specifying existing interface
|
2012-11-17 19:44:25 +01:00 |
|
Sebastien Bourdeauducq
|
86090e1cbd
|
bus/asmibus: swap port position to be consistent with wishbone API
|
2012-11-17 19:42:39 +01:00 |
|
Sebastien Bourdeauducq
|
ece786d6aa
|
bus/wishbone: allow specifying existing interface
|
2012-11-17 19:42:06 +01:00 |
|
Sebastien Bourdeauducq
|
d0d4c48098
|
bus/transactions: add busname parameter
|
2012-11-17 19:36:08 +01:00 |
|
Sebastien Bourdeauducq
|
897a2e3f9c
|
actorlib/sim: split TokenExchanger
|
2012-11-17 14:15:51 +01:00 |
|
Sebastien Bourdeauducq
|
eb156af20c
|
pytholite/io: support token pull
|
2012-11-16 23:48:41 +01:00 |
|
Sebastien Bourdeauducq
|
dd9a102a78
|
pytholite/io: support token push
|
2012-11-16 19:24:45 +01:00 |
|
Sebastien Bourdeauducq
|
bf5ce8dc20
|
pytholite: move expression and register handling to separate modules
|
2012-11-11 23:48:23 +01:00 |
|
Sebastien Bourdeauducq
|
f59fd69e34
|
pytholite/compiler: recognize composite I/O pattern
|
2012-11-11 18:03:16 +01:00 |