enjoy-digital
70c5be6fb8
Merge pull request #1090 from gregdavill/jtag_ecp5_fix
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soc.jtag.ecp5: Support all ECP5 devices
2021-10-27 14:34:30 +02:00
Greg Davill
5faddcdb50
soc.jtag.ecp5: Support all ECP5 devices
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- "LFE5UM" devices exclude these without serdes
2021-10-27 20:36:31 +10:30
Florent Kermarrec
296688b2d8
cores/jtag/ECP5JTAG: Fix LUT4's INIT to create a buffer instead of inverter, thanks @gregdavill.
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Avoid restriction to even number for tck_delay_luts.
2021-10-27 11:01:09 +02:00
Florent Kermarrec
0b40d78b0d
cores/jtag/ECP5JTAG: Delay TCK with LUT4 to avoid sys_clk/jtag_clk relationship and support higher jtag_clk frequencies.
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Tested succesfully on the ButterStick with 75MHz sys_clk/25MHz jtag_clk.
Current tck_delay_luts is abritrary and should probably be adjusted.
2021-10-26 19:59:02 +02:00
Florent Kermarrec
16af95e424
cores/jtag/ECP5JTAG: Minor cleanup, add Gabriel to copyrights ( #797 ).
2021-10-26 18:07:09 +02:00
enjoy-digital
d4ee5d1399
Merge pull request #1087 from gregdavill/jtag-ecp5
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Add JTAG support on ECP5
2021-10-26 18:00:50 +02:00
Florent Kermarrec
12d53790a9
test/test_cpu: Prepare microwatt/lm32 test.
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microwatt: Still requires Yoys/GHDL-Synth installation.
lm32: Still requires prebuilt toolchain.
2021-10-26 16:37:38 +02:00
enjoy-digital
ccef999772
Merge pull request #1088 from enjoy-digital/ci-openrisc
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CI: Add OpenRISC GCC toolchain installation.
2021-10-26 16:30:56 +02:00
Florent Kermarrec
e617f52e34
test/test_cpu: Comment test_mor1kx for now (test work but issue seems related to the pre-built toolchain).
2021-10-26 16:30:02 +02:00
Florent Kermarrec
07b856d01e
cores/cpu/mor1kx: Fix gcc_triple (Was duplicated).
2021-10-26 16:06:10 +02:00
Florent Kermarrec
5e2db8e712
README: Update installation instruction (still work with previous ones but just to encourage users to switch).
2021-10-26 15:50:40 +02:00
Florent Kermarrec
cb9f0fb1b0
ci/test_cpu: Install OpenRISC GCC toolchain in CI and add mor1kx to test_cpu.
2021-10-26 15:45:43 +02:00
Florent Kermarrec
f6562195d5
litex_setup: Make compat_args optional, fix dev mode.
2021-10-26 15:16:43 +02:00
Florent Kermarrec
dab4845c9b
litex_setup: Handle download of PowerPC/OpenRisc GCC toolchains.
2021-10-26 15:11:28 +02:00
Florent Kermarrec
71b319eeaf
litex_setup: Switch to argparse and handle retro-compatibility.
2021-10-26 14:37:08 +02:00
Greg Davill
bd65cf6b30
soc.cores.jtag: Add ECP5JTAG
2021-10-26 22:36:23 +10:30
Florent Kermarrec
e26904bd98
README: Add LiteSPI/LiteHyperBus.
2021-10-26 12:45:15 +02:00
Florent Kermarrec
e3b5734cb1
litex_setup: Add common gcc_toolchain_download function and use it to download the different toolchains.
2021-10-26 12:40:43 +02:00
Florent Kermarrec
152bbd67ed
ci: GITHUB_ACTIONS export not currently required.
2021-10-26 12:24:56 +02:00
Florent Kermarrec
81da5c1bb6
ci: Increase similarities with LiteDRAM CI.
2021-10-26 12:15:13 +02:00
Florent Kermarrec
d6ce5d3afa
litex_setup: Fix missing repos.
2021-10-26 12:01:21 +02:00
Florent Kermarrec
a6d076f810
litex_setup: Reorganize code with functions.
2021-10-26 11:36:38 +02:00
Florent Kermarrec
5c0e951dc3
litex_setup: Cleanup/Simplify.
2021-10-26 10:49:34 +02:00
Florent Kermarrec
71a91eac15
test: Rename test_boot.py to test_cpu.py.
2021-10-26 08:35:16 +02:00
Florent Kermarrec
9b4c7e8288
README/litex_setup: Remove reference to LiteVideo to encourage use of LiteX's VideoTerminal/Out core.
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LiteVideo is not longer maintained, does not have CI and is messy (code is ~10 years old where we were
still experimenting the innovative approach with Migen). The core is kept since can be useful as reference
for Video Input and for projects using it but it is not recommended for new designs.
2021-10-26 08:21:00 +02:00
enjoy-digital
07bd8ed65b
Merge pull request #1082 from enjoy-digital/mithro-patch-1
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Fix a misspelling in README
2021-10-26 07:51:35 +02:00
Tim Ansell
a6d8679f78
Fix a misspelling
2021-10-25 17:20:48 -07:00
Florent Kermarrec
8c62bb8d2e
fhdl/memory_efinix: Add efx to transformed memories to avoid conflicts.
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Fix the crash with the LiteX identifier.
2021-10-25 19:32:18 +02:00
Florent Kermarrec
7914923d2d
soc/build: Avoid no_we mode on RAMs and move specialization of Efinix memories to fhdl.
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Specialization still only support 32-bit RAMs and will still need to be refactored.
2021-10-25 19:08:09 +02:00
Florent Kermarrec
a3678c1298
build/efinix/ifacewriter: Remove add_ddr_xml (too early to support it).
2021-10-25 18:17:07 +02:00
Florent Kermarrec
0ed3803291
cores/clock/efinix_trion: Switch to excluded_ios and simplify create_clkout.
2021-10-25 18:14:45 +02:00
Florent Kermarrec
fff5895130
build/efinix: Avoid deleting IOs from platform (too complicated), just use an excluded IOs list.
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Also remove generic_platform's delete that was only used for here.
2021-10-25 18:13:56 +02:00
Florent Kermarrec
5dc377eda1
clock/efinix_trion: Cleanup PLL block, fix reset polarity and always enable it.
2021-10-25 17:49:39 +02:00
Florent Kermarrec
36b26006a4
fhdl/verilog: Only collect IOs when ios set is empty.
2021-10-25 17:17:50 +02:00
Florent Kermarrec
7662ec5531
clock/efinix_trion: Replace ' with ".
2021-10-25 17:11:10 +02:00
Florent Kermarrec
cfc0b1d337
clock/efinix_trion: Remove count (this will have to be correctly implemented).
2021-10-25 17:09:47 +02:00
Florent Kermarrec
8dc727b514
build/efinix/common: Cleanup EfinixTristateImpl.
2021-10-25 15:00:43 +02:00
Florent Kermarrec
ce1660da4d
generic_platform/fhdl/verilog: Move IOs collection to fhdl/verilog.
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IOs can be genererated while lowering specials on Efinix FPGAs.
2021-10-25 14:40:21 +02:00
Florent Kermarrec
0784fd0396
build/efinix/__init__.py: Remove EfinixDDR import.
2021-10-25 12:43:28 +02:00
Florent Kermarrec
c04753bd3a
build/efinix: Remove ddr/rgmii/video cores support (will have to be integrated properly in LiteDRAM/LiteEth/LiteX and integrated in LiteX-Boards).
2021-10-25 12:32:30 +02:00
Florent Kermarrec
cab1742cf0
build/efinix: Remove useless () on classes.
2021-10-25 12:23:36 +02:00
Florent Kermarrec
e6f7dbe69b
build/efinix/dbparser: Fix syntax error.
2021-10-25 11:36:23 +02:00
enjoy-digital
a083c34e47
Merge pull request #1078 from trabucayre/efinix_pllv1
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efinix: pll v1 (T4/T8) support
2021-10-25 11:26:46 +02:00
Florent Kermarrec
47b3c9bc08
soc/interconnect/packet: Remove last_be support in LiteX, specialized Packetizer/Depacketizer have been moved to LiteEth to simplify development and avoid eventual regresion on others cores.
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As seen during the last LiteEth developments, last_be data qualifier is not easy to handle correctly and should be replaced by a simpler data qualifier (similar to AXI's tkeep/tstrb). It will
be easier to do so by having a local copy of Packetizer/Depacketizer directly in LiteEth (still with last_be support) and work on the simpler data qualifier in LiteX (and test it on LitePCIe).
2021-10-25 11:17:36 +02:00
enjoy-digital
96101521be
Merge pull request #1079 from lschuermann/dev/xgmii-rx-fcs
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litex_sim/xgmii_ethernet: fix RX frame check sequence generation
2021-10-25 10:30:05 +02:00
Leon Schuermann
f2a622975a
litex_sim/xgmii_ethernet: fix RX frame check sequence generation
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The rewritten XGMII Ethernet module generates proper frame check
sequences (FCS) on Ethernet frames received by the simulation, such
that the unmodified MAC pipeline including CRC checking can be
used. However, the byte order of the generated frame check sequence
has been inverted. This becomes apparent when one specifies that the
CRC should be calculated in the LiteX BIOS.
This fixes the byte order to be correct. The similar GMII Ethernet
module did not contain this mistake.
Fixes: 7b533a032d
("litex_sim: rewrite XGMII verilator...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-10-25 08:57:36 +02:00
Gwenhael Goavec-Merou
3c209c6c1f
efinix: pll v1 (T4/T8) support
2021-10-24 17:39:57 +02:00
Navaneeth Bhardwaj
2886fe1701
Add bios test mode for CI ( #1076 )
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* Add bios test mode for CI
This enables to test the booting of each CPU configurations with the bios in Verilator simulation.
2021-10-24 12:08:58 +02:00
Florent Kermarrec
8e448592f0
interconnect/packet: Revert old last/ready logic handling (new one breaks test_packet) and comment out test_packet2 tests (does not seems to be working with previous last/ready handling).
2021-10-23 18:21:47 +02:00
Florent Kermarrec
59fd2d31c7
test/test_packet2: Fix imports.
2021-10-23 17:54:00 +02:00