Sebastien Bourdeauducq
320dffb4ac
sim: memory access from generators
2015-09-20 14:52:26 +08:00
Sebastien Bourdeauducq
1861ae9d01
fhdl/specials: MemoryPort.clock should always be a ClockSignal
2015-09-19 23:21:24 +08:00
Sebastien Bourdeauducq
e940c6d9b9
fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem
2015-09-15 12:38:02 +08:00
Sebastien Bourdeauducq
336728413a
simplify imports, migen.fhdl.std -> migen
2015-09-12 19:34:07 +08:00
Florent Kermarrec
d77a5fc5ac
fhdl/specials: add Keep SynthesisDirective
2015-06-23 16:14:42 +02:00
Florent Kermarrec
f97d7ff44c
global: pep8 (E261, E271)
2015-04-13 21:21:30 +02:00
Florent Kermarrec
1051878f4c
global: pep8 (E302)
2015-04-13 20:45:35 +02:00
Florent Kermarrec
17e5249be0
global: pep8 (replace tabs with spaces)
2015-04-13 20:07:07 +02:00
Sebastien Bourdeauducq
e1702c422c
introduce conversion output object (prevents file IO in FHDL backends)
2015-04-08 20:28:23 +08:00
Sebastien Bourdeauducq
dc88295338
Revert "migen/fhdl: pass fdict filename --> contents to specials"
...
This reverts commit ea04947519
2015-03-30 19:41:13 +08:00
Sebastien Bourdeauducq
b1c811a3d1
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"
...
This reverts commit 95cfc444e6
2015-03-30 19:41:04 +08:00
Florent Kermarrec
95cfc444e6
migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method
2015-03-30 11:37:59 +02:00
Florent Kermarrec
ea04947519
migen/fhdl: pass fdict filename --> contents to specials
2015-03-30 11:37:57 +02:00
Florent Kermarrec
5a9afee234
fhdl/specials/memory: use $readmemh to initialize memories
2015-03-18 15:27:01 +01:00
Florent Kermarrec
b7d7fe1a4c
fhdl/special: add optional synthesis directive (needed by Synplify Pro)
2015-03-17 14:59:05 +01:00
Florent Kermarrec
dbaeaf7833
remove trailing whitespaces
2014-10-17 17:08:46 +08:00
Sebastien Bourdeauducq
c13fe1bc63
specials/Memory: allow for more flexibility in memory port signals
2013-12-12 17:36:17 +01:00
Robert Jordens
8d3d61ba98
fhdl.size: rename to bitcontainer
2013-12-03 22:51:52 +01:00
Sebastien Bourdeauducq
fa741f54fd
specials/Instance: add PreformattedParam
2013-11-25 12:09:51 +01:00
Sebastien Bourdeauducq
cec8fc4ca4
fhdl/specials/Instance: fix item sorting
2013-07-26 14:00:29 +02:00
Sebastien Bourdeauducq
b96eb339af
fhdl: compact Instance syntax
2013-07-25 20:34:19 +02:00
Sebastien Bourdeauducq
bac62a32a9
Make memory ports part of specials
...
This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
2013-05-28 16:11:34 +02:00
Sebastien Bourdeauducq
70ffe86356
New migen.fhdl.std to simplify imports + len->flen
2013-05-22 17:11:09 +02:00
Sebastien Bourdeauducq
fee228a09f
fhdl/specials/memory: do not write address register for async reads
2013-04-25 13:30:05 +02:00
Sebastien Bourdeauducq
574becc1fc
fhdl/specials: clean up clock domain handling
2013-03-26 11:58:34 +01:00
Sebastien Bourdeauducq
7a06e9457c
Lowering of Special expressions + support ClockSignal/ResetSignal
2013-03-18 18:36:50 +01:00
Sebastien Bourdeauducq
7b49fd9386
fhdl/specials: fix rename_clock_domain declarations
2013-03-15 19:47:01 +01:00
Sebastien Bourdeauducq
4ada2ead05
fhdl/specials/Memory: automatic name#
2013-03-12 15:58:39 +01:00
Sebastien Bourdeauducq
a81781f589
fhdl/specials: allow setting memory name
2013-02-25 23:14:03 +01:00
Sebastien Bourdeauducq
55ab01f928
fhdl/specials/Instance: _printintbool -> verilog_printexpr
2013-02-24 13:08:01 +01:00
Sebastien Bourdeauducq
38664d6e16
fhdl: inline synthesis directive support
2013-02-22 19:10:02 +01:00
Sebastien Bourdeauducq
49cfba50fa
New 'specials' API
2013-02-22 17:56:35 +01:00
