Florent Kermarrec
|
38e8ea683e
|
s6ddrphy: add support for differential dqs and optional cs_n
|
2013-07-20 12:21:59 +02:00 |
Sebastien Bourdeauducq
|
ea65aaaddd
|
s6ddrphy: cleanup
|
2013-07-17 13:58:58 +02:00 |
|
Florent Kermarrec
|
fb06d803e1
|
s6ddrphy: revert CAS LATENCY 3 (configurable CAS Latency was buggy)
|
2013-07-17 13:11:25 +02:00 |
|
Sebastien Bourdeauducq
|
26ff6f2a9c
|
s6ddrphy: style and other minor fixes
|
2013-07-10 20:39:53 +02:00 |
|
Florent Kermarrec
|
60f1585fef
|
use Migen s6ddrphy, generate sdram init_sequence in cif.py
|
2013-07-10 19:56:09 +02:00 |
|
Sebastien Bourdeauducq
|
611c4192b1
|
Use migen.fhdl.std
|
2013-05-22 17:10:13 +02:00 |
|
Sebastien Bourdeauducq
|
1e860c7472
|
Use new Mibuild generic_platform API
|
2013-03-26 17:57:17 +01:00 |
|
Sebastien Bourdeauducq
|
48aae9bee5
|
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
|
2013-03-18 17:44:01 +01:00 |
|
Sebastien Bourdeauducq
|
a9b723568a
|
Use new module, autoreg and eventmanager Migen APIs
|
2013-03-10 19:32:38 +01:00 |
|
Sebastien Bourdeauducq
|
0caac2246d
|
Use new 'specials' API
|
2013-02-24 13:07:25 +01:00 |
|
Sebastien Bourdeauducq
|
5649e88a90
|
Use Mibuild
|
2013-02-11 18:23:06 +01:00 |
|
Sebastien Bourdeauducq
|
8bf6945dfd
|
Use new bitwidth/signedness system
|
2012-11-29 23:38:04 +01:00 |
|
Sebastien Bourdeauducq
|
c86dd3cbef
|
Define clock domains instead of passing extra clocks as regular signals
|
2012-09-11 00:21:07 +02:00 |
|
Sebastien Bourdeauducq
|
5931c5eb59
|
Basic support for new clock domain and instance API
|
2012-09-10 23:47:06 +02:00 |
|
Sebastien Bourdeauducq
|
19b1cc2529
|
Remove uses of pads, new constraints system
|
2012-04-02 19:22:17 +02:00 |
|
Sebastien Bourdeauducq
|
b4e041ecf1
|
s6ddrphy: write path OK in simulation
|
2012-02-20 23:55:20 +01:00 |
|
Sebastien Bourdeauducq
|
f35cd4a85b
|
Prepare for new DDR PHY
|
2012-02-19 18:43:42 +01:00 |
|
Sebastien Bourdeauducq
|
c387ce7ce5
|
Map DDR PHY controls in CSR
|
2012-02-17 17:34:59 +01:00 |
|
Sebastien Bourdeauducq
|
5d1dad583b
|
Connect DDR PHY
Doesn't do much for the moment, just to check synthesis/P&R.
|
2012-02-17 11:04:44 +01:00 |