771897fa37
cpu/rocket: naturally align data defined in crt0.S
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The startup code accesses this data using sd/ld instructions, which
require that the address being accessed is 8-byte aligned.
The .dword asm directive does NOT imply any alignment, so we need
to force it using the .align directive.
2021-10-04 15:22:13 +02:00
cb6861e1c8
build: Add initial/minimal QuickLogic build support.
2021-10-01 11:42:56 +02:00
16702c44fe
Merge pull request #1055 from gsomlo/gls-pico-warn-64
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64-bit follow-up for picolibc warning fixes
2021-10-01 10:49:07 +02:00
d92f10dfb0
64-bit follow-up for picolibc warning fixes
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Providing "uint32_t" to printf's "%ld" results in warnings on 64-bit
builds: use "unsigned long" instead.
2021-09-30 20:26:40 -04:00
77283d3d8d
software: Fix picolibc compilation warnings.
2021-09-30 19:24:58 +02:00
841732f38f
software/liblitesata: Fix compilation with picolibc.
2021-09-30 18:56:01 +02:00
7b7fd25d5d
Merge pull request #1054 from niw/fix_disk_read_arg_name
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FIX: arg name is changed.
2021-09-30 17:44:33 +02:00
abcf5f1d7b
FIX: arg name is changed.
2021-09-30 02:56:19 -07:00
47e4a1b437
tools/litex_term: Avoid staying in safe mode on next upload when previous calibration failed.
2021-09-30 10:11:48 +02:00
4563ccae18
Merge pull request #1052 from developandplay/patch-5
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Add ninja to toolchain setup
2021-09-30 09:33:28 +02:00
5e2d03dad7
Add ninja to toolchain setup
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In addition to meson I had to install ninja for the picolibc update.
Not sure if it was just an issue on my system but wanted to flag it.
2021-09-30 00:10:45 +02:00
5661480409
tools/litex_term: Add automatic inter-frame delay calibration and --safe mode.
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By default, litex_term will now automatically try to find the best inter-frame delay/payload length
parameters to optimize upload speed. The --safe mode can also be used to disable outstanding frames
(and then wait ack for each frame), it will be slow on regular UARTs (that have high round-trip
latencis) but should always work.
2021-09-29 18:41:06 +02:00
80cb53fb04
software/bios/boot: Allow frame reception to time out during serial boot and do some cleanup/add comments.
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Allowing the serial boot to time out during frame reception allows doing test on the Host side to
calibrate the minimum inter-frame delay and maximum payload length.
In the future, we should probably compute the CRC directly during frame reception and do the mempcpy
of frame N during the reception of frame N+1 to avoid these inter-frame constraints.
2021-09-29 18:33:59 +02:00
5a35aa9df6
software/libliteeth: Fix missing prototype warnings.
2021-09-28 17:46:23 +02:00
7bf6db5f9d
README: Add meson package install.
2021-09-28 16:27:30 +02:00
9a931324c2
get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed.
2021-09-28 16:27:13 +02:00
a5b3ab1bc9
Merge pull request #1051 from antmicro/picolibc-updates
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Picolibc updates
2021-09-28 16:01:29 +02:00
9f1108c2fc
libc: refactor picolibc build deps
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:30 +02:00
b9c4d7ba51
libc: add _impure_ptr definition
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:17:08 +02:00
22f50ec7ff
libc: add errno include
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This solves missing `__errno` symbol linker errors
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-28 15:16:34 +02:00
a588c3b830
software/libc: Disable Atomics support on fgetc/ungetc since seems broken (at least on Rocket).
2021-09-28 14:51:02 +02:00
99d8bbc3bc
Merge pull request #1050 from antmicro/fix-litex_setup_url
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Revert litex_setup_url change
2021-09-28 14:28:29 +02:00
061b89beff
cpu/picolibc: Add family property to CPUs and directly use it for picolibc.
2021-09-28 14:20:13 +02:00
b451f102c6
software/libc/stdio: Simplify/Cleanup.
2021-09-28 14:04:24 +02:00
12c93ea895
litex_sim: Generate gtkw_savefile only with --trace.
2021-09-28 13:32:12 +02:00
c0e7e3acd3
Revert litex_setup_url change
2021-09-28 12:35:20 +02:00
782744bae3
tools/litex_sim/generate_gtkw_savefile: Check main_ram presence.
2021-09-28 10:02:17 +02:00
de738e153d
tools/litex_sim: Avoid double build iteration with pre_run_callback function.
2021-09-28 09:58:43 +02:00
c98c777bed
integration/builder: Avoid picolibc/compiler_rt dependencies when not using the LiteX BIOS & minor cleanups.
2021-09-28 08:57:49 +02:00
29fb1c48d0
Merge pull request #1046 from antmicro/libc-deps
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software: libc: fix Makefile dependecies
2021-09-27 14:56:25 -07:00
d101ef7ed0
software: libc: fix Makefile dependecies
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2021-09-27 23:05:54 +02:00
01a906add7
software/liblitesdcard: Fix compilation with picolibc.
2021-09-27 18:56:18 +02:00
727d898a6c
software/libliteeth: Update/Fix compilation with picolibc.
2021-09-27 18:54:28 +02:00
54623dbe26
litex_setup: Update picolibc url (now on litex-hub).
2021-09-27 18:15:10 +02:00
7119dd8098
Merge pull request #1023 from lschuermann/dev/litex-sim-gmii-xgmii
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litex_sim: add support for simulated GMII & XGMII, rewrite XGMII module
2021-09-27 17:48:44 +02:00
87f7f3bc45
Merge branch 'master' into dev/litex-sim-gmii-xgmii
2021-09-27 17:47:26 +02:00
9ab82cacda
soc/add_ethernet/etherbone: Fix conflicts/Update.
2021-09-27 17:43:39 +02:00
17abdfd12d
Merge pull request #1043 from enjoy-digital/rocket-remove-reset-inserter
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cpu/rocket/core: Remove ResetInserter on adapters.
2021-09-27 16:34:46 +02:00
49f8652f91
ci: Install meson (now required by picolibc).
2021-09-27 16:19:56 +02:00
746d698b49
litex_setup.py: Revert LiteX url.
2021-09-27 16:15:16 +02:00
3d32ac3d2e
software: Avoid libase renaming to libutils/libcomm and keep readchar/putsnonl retro-compatibility.
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We'll maybe do it but that's probably not the right time. We have to make
the picolibc switch as smooth as possible for users (and so avoid update
as much as possible).
In the long term, it would be good to provide a LiteX C SDK, so we'll make
eventual changes when doing this.
2021-09-27 16:15:13 +02:00
ae1d43b965
software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile.
2021-09-27 16:14:55 +02:00
c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement
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Replace libbase with picolibc
2021-09-27 16:05:24 +02:00
944732aa19
soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone.
2021-09-27 15:46:19 +02:00
ce0551b44a
cpu/rocket/core: Remove ResetInserter on adapters.
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Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
2021-09-27 09:05:46 +02:00
c43132f81f
Merge pull request #1040 from gsomlo/gls-rocket-smp
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Rocket SMP support
2021-09-23 10:56:06 +02:00
07e47d9357
cpu/rocket: add quad-core (smp) variants
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- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
2021-09-22 16:59:04 -04:00
901b19828c
cpu/rocket: include core count as per-variant parameter
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Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
2021-09-22 16:58:11 -04:00
e6aaa40d2d
cpu/rocket: bios support for SMP
2021-09-22 13:51:18 -04:00
2bc8124114
cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic)
2021-09-22 13:51:18 -04:00
Jakub Piecuch
Florent Kermarrec
Gabriel Somlo
Yoshimasa Niwa
developandplay
Karol Gugala
Michal Sieron
Tim Ansell