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Author	SHA1	Message	Date
Florent Kermarrec	78fb0fb9dc	tools/litex_read_verilog: also delete yosys_v2j.ys	2019-09-24 08:49:00 +02:00
Benjamin Herrenschmidt	0ea7a1fd05	soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty ... For example a standalone controller with no exposed CSRs (probably not a very useful configuration but I really don't like python backtraces) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2019-09-24 08:41:59 +02:00
enjoy-digital	742da31bc0	Merge pull request #264 from antmicro/mor1kx_linux ... Enable to run Linux on mork1x	2019-09-23 23:19:45 +02:00
Florent Kermarrec	06d0806494	soc_core: set csr to 0x00000000 when there is no wishbone	2019-09-23 15:57:14 +02:00
Florent Kermarrec	ad8830d977	soc_sdram: Don't add the L2 Cache when there's no wishbone bus	2019-09-23 15:53:07 +02:00
Filip Kokosinski	5844376d53	soc_core: adapt memory map for mainline Linux with mor1kx ... Mainline Linux expects it to be loaded at the physical address of 0x0. Change the MAIN_RAM base address to 0x0 and update exception vector during the booting process.	2019-09-23 15:34:52 +02:00
Filip Kokosinski	201218b2c3	boards/targets: increase integrated ROM size if EthernetSoC is used ... Currently section '.rodata' of the LiteX BIOS doesn't fit in the 'rom' region if mor1kx is used with EthernetSoC. Increase the integrated ROM size from 0x8000 to 0x10000 in EthernetSoC.	2019-09-23 15:34:34 +02:00
Florent Kermarrec	ae38fd4244	soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter	2019-09-23 12:59:43 +02:00
Florent Kermarrec	8c979565a8	soc_sdram: change l2_size checks order	2019-09-23 10:15:27 +02:00
Florent Kermarrec	a9acab99b3	soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals)	2019-09-23 09:58:47 +02:00
Florent Kermarrec	dde6dd027b	integration/builder: avoid specific _generate_standalone_includes	2019-09-23 09:26:47 +02:00
Benjamin Herrenschmidt	735ea196dd	This will allow it to be built for microwatt out of tree ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2019-09-23 08:40:54 +02:00
Benjamin Herrenschmidt	c28086cde8	soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2019-09-23 08:35:50 +02:00
Benjamin Herrenschmidt	f909e4d706	integration/builder: When the CPU is "None", we used to not generate any code. ... With this change, we will now generate csr.h and sdram_phy.h, which will be needed by the initialization code running on the host CPU. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2019-09-23 08:31:21 +02:00
enjoy-digital	8b7d8217a0	Merge pull request #263 from xobs/spi-flash-csrfield ... spi_flash: document register fields	2019-09-20 08:28:19 +02:00
Sean Cross	1a6dddd57c	spi_flash: document register fields ... Document the various fields present in the SPI flash bitbang interface. This adds documentation for the Single and DualQuad modules. Signed-off-by: Sean Cross <sean@xobs.io>	2019-09-20 12:42:43 +08:00
enjoy-digital	4f659ba422	Merge pull request #262 from jersey99/master ... vivado just needs to be in the path for the programmer as well	2019-09-20 06:25:57 +02:00
Vamsi K Vytla	9ea11cf5ab	vivado just needs to be in the path for the programmer as well	2019-09-19 20:35:55 -07:00
enjoy-digital	430fee4dbd	Merge pull request #261 from xobs/event-documentation ... csr_eventmanager: add `name` and `description` args	2019-09-19 11:40:55 +02:00
Sean Cross	60d8572c3e	csr_eventmanager: add name and description args ... Add `name` and `description` as optional arguments to the various EventSource types. These default to `None`, so this should be a backwards-compatible change. Use the same trick as CSRs, where we default the `name` to be the instantiated object name as read from the Migen `get_obj_var_name()` call. Signed-off-by: Sean Cross <sean@xobs.io>	2019-09-19 17:23:03 +08:00
Florent Kermarrec	e2c78572a2	cores/timer: add general documentation on Timer implementation and behavior.	2019-09-19 09:27:24 +02:00
Florent Kermarrec	e97c1e36fb	soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower	2019-09-19 05:36:57 +02:00
Florent Kermarrec	99ed0877ac	csr: add description to CSRStorage/CSRStatus attributes (thanks xobs)	2019-09-18 10:47:54 +02:00
Florent Kermarrec	f2e84a5800	soc/cores/timer: fix typo (thanks xobs)	2019-09-18 10:45:38 +02:00
Florent Kermarrec	28885064f7	soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident.	2019-09-18 10:14:47 +02:00
enjoy-digital	f1139c36b4	Merge pull request #259 from xobs/document-timer ... timer: add documentation	2019-09-18 09:36:53 +02:00
Sean Cross	cb7d941aaa	timer: add documentation ... Now that CSRs have documentation support, add documentation to the basic `Timer` module. Signed-off-by: Sean Cross <sean@xobs.io>	2019-09-18 15:06:20 +08:00
Florent Kermarrec	cca0478a5e	soc/cores/spi: use new CSRField (no functional change)	2019-09-16 17:02:55 +02:00
Florent Kermarrec	80b2bef387	soc/cores/bitbang: use new CSRField (no functional change)	2019-09-16 16:56:00 +02:00
enjoy-digital	3dc8d29498	Merge pull request #257 from enjoy-digital/csr_fields ... soc/interconnect/csr: add CSRField/documentation support, do some simplification on CSRStorage	2019-09-16 09:16:20 +02:00
Florent Kermarrec	9bda614a3e	csr: update copyrights	2019-09-16 08:49:00 +02:00
Florent Kermarrec	29134cc659	csr: more documentation	2019-09-16 08:45:29 +02:00
Florent Kermarrec	74e756aa30	csr/CSRStorage: remove storage_full (was only needed by alignment_bits)	2019-09-16 08:38:26 +02:00
Florent Kermarrec	5dc440e80d	csr: use IntEnum for CSRAccess	2019-09-16 08:36:25 +02:00
Florent Kermarrec	d2646f138e	csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful	2019-09-15 19:47:48 +02:00
Florent Kermarrec	8e14694eb5	csr/fields: document, add separators, 100 characters per line	2019-09-15 19:11:25 +02:00
Florent Kermarrec	4e84729cf9	csr/fields: add access parameter	2019-09-14 22:16:18 +02:00
Florent Kermarrec	23b01f8f02	csr/fields: add pulse mode support	2019-09-14 21:49:34 +02:00
Florent Kermarrec	8c080e5fb6	soc/interconnect/csr: add initial field support	2019-09-13 20:01:31 +02:00
Florent Kermarrec	c120f6d457	build/openocd: add set_qe parameter to flash ... QE bit is not set on blank SPI flashes and need to be set when SPI X4 is enabled in the bistream to load the FPGA.	2019-09-12 17:07:56 +02:00
Florent Kermarrec	6a0a1c9d87	tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example)	2019-09-12 10:21:37 +02:00
Florent Kermarrec	16b6b357ca	soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found	2019-09-11 18:30:28 +02:00
Florent Kermarrec	62f53d5035	soc/integration/builder: call do_exit with vns when build is done.	2019-09-10 12:41:05 +02:00
Florent Kermarrec	cb5f1467cf	Merge branch 'master' of http://github.com/enjoy-digital/litex	2019-09-09 15:12:24 +02:00
Florent Kermarrec	004c96b508	soc/itnegration: update litedram	2019-09-09 15:12:08 +02:00
enjoy-digital	a7b5c18523	Merge pull request #255 from sergachev/fix-crc32 ... fix crc32	2019-09-09 13:38:29 +02:00
Ilia Sergachev	2400f0f43d	fix crc32	2019-09-09 13:19:43 +02:00
Florent Kermarrec	19f58dd971	interconnect/wishbone: add FlipFlop to allow UpConverter to be used ... Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up	2019-09-09 11:47:36 +02:00
Florent Kermarrec	bd6ec63be4	build/openocd: add stream method for JTAG UART	2019-09-06 11:57:18 +02:00
Florent Kermarrec	b356204f95	soc_core: add JTAG UART support (uart_name="jtag_uart)	2019-09-06 11:56:42 +02:00