Sebastien Bourdeauducq
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c4d9734e53
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README: update
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2013-03-11 20:29:47 +01:00 |
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Sebastien Bourdeauducq
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80970b203c
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bus/asmibus: use implicit finalization
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2013-03-11 17:11:59 +01:00 |
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Sebastien Bourdeauducq
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b042757187
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Fix Register name conflict between Pytholite and Bank
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2013-03-10 19:47:21 +01:00 |
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Sebastien Bourdeauducq
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f93695f60e
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bank/eventmanager: use module and autoreg
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2013-03-10 19:29:05 +01:00 |
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Sebastien Bourdeauducq
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174e8cb8d6
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bus/asmibus: use fhdl.module API
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2013-03-10 19:28:22 +01:00 |
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Sebastien Bourdeauducq
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17e0dfe120
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fhdl/module: replace autofragment
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2013-03-10 19:27:55 +01:00 |
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Sebastien Bourdeauducq
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cddbc1157d
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bank/description/AutoReg: check that get_memories and get_registers are callable
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2013-03-10 18:11:29 +01:00 |
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Sebastien Bourdeauducq
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68fe4c269c
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bank/csrgen: BankArray
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2013-03-10 00:45:16 +01:00 |
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Sebastien Bourdeauducq
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f1474420df
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bank/description: AutoReg
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2013-03-10 00:43:16 +01:00 |
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Sebastien Bourdeauducq
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d0676e2dd1
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migen/fhdl/autofragment: factorize
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2013-03-09 23:23:24 +01:00 |
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Sebastien Bourdeauducq
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d0d2df3c4b
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fhdl/autofragment: remove legacy functions
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2013-03-09 23:05:45 +01:00 |
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Sebastien Bourdeauducq
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72fb6fd6bd
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fhdl/tools/flat_iteration: generalize
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2013-03-09 23:03:15 +01:00 |
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Sebastien Bourdeauducq
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f53acb92e7
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fhdl/autofragment: fix submodules
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2013-03-09 21:15:38 +01:00 |
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Sebastien Bourdeauducq
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6da8eb906f
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fhdl/autofragment: empty build_fragment by default
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2013-03-09 19:10:47 +01:00 |
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Sebastien Bourdeauducq
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2b8dc52c13
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Use common definition for FinalizeError
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2013-03-09 19:03:13 +01:00 |
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Sebastien Bourdeauducq
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b75fb7f97c
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csr/SRAM: support for writes with memory widths larger than bus words
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2013-03-09 00:50:57 +01:00 |
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Sebastien Bourdeauducq
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6fa30053bf
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fhdl/verilog: tristate outputs are always wire
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2013-03-06 11:30:52 +01:00 |
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Sebastien Bourdeauducq
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9b4ca987e0
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bus/csr: support memories with larger word width than the bus (read only)
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2013-03-03 19:27:13 +01:00 |
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Sebastien Bourdeauducq
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bb5ee8d3bd
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fhdl/autofragment: bugfixes + add auto_attr
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2013-03-03 17:53:06 +01:00 |
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Sebastien Bourdeauducq
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cc8118d35c
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fhdl/autofragment: FModule
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2013-03-02 23:30:54 +01:00 |
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Sebastien Bourdeauducq
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d2491828a4
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csr/SRAM: prefix page register with memory name
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2013-03-01 12:06:12 +01:00 |
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Sebastien Bourdeauducq
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c10622f5e2
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fhdl/verilog: insert reset before listing signals
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2013-02-27 18:10:04 +01:00 |
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Sebastien Bourdeauducq
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d2cbc70190
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bank/description: memprefix
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2013-02-25 23:14:15 +01:00 |
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Sebastien Bourdeauducq
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a81781f589
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fhdl/specials: allow setting memory name
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2013-02-25 23:14:03 +01:00 |
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Sebastien Bourdeauducq
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425de02f42
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uio/ioo: fix specials
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2013-02-25 23:13:38 +01:00 |
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Sebastien Bourdeauducq
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55ab01f928
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fhdl/specials/Instance: _printintbool -> verilog_printexpr
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2013-02-24 13:08:01 +01:00 |
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Sebastien Bourdeauducq
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c2d54f481f
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examples/psync: cleanup
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2013-02-23 19:14:31 +01:00 |
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Sebastien Bourdeauducq
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6abac5907b
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examples/basic/psync: demonstrate the new features
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2013-02-23 19:04:11 +01:00 |
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Sebastien Bourdeauducq
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a878db1e3c
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genlib: clock domain crossing elements
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2013-02-23 19:03:35 +01:00 |
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Sebastien Bourdeauducq
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7c4e6c35e5
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fhdl/verilog: support special lowering and overrides
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2013-02-23 19:03:16 +01:00 |
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Sebastien Bourdeauducq
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3a591c358c
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examples/fir: better filter
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2013-02-22 23:19:56 +01:00 |
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Sebastien Bourdeauducq
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f9acee4e68
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corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
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Sebastien Bourdeauducq
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38664d6e16
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fhdl: inline synthesis directive support
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2013-02-22 19:10:02 +01:00 |
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Sebastien Bourdeauducq
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587f50cf90
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doc: new 'specials' API
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2013-02-22 18:12:42 +01:00 |
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Sebastien Bourdeauducq
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49cfba50fa
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New 'specials' API
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2013-02-22 17:56:35 +01:00 |
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Sebastien Bourdeauducq
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e82ea19cdc
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doc: tristates
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2013-02-19 17:52:57 +01:00 |
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Sebastien Bourdeauducq
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1b18194b1d
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fhdl: TSTriple
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2013-02-19 17:26:02 +01:00 |
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Sebastien Bourdeauducq
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dc93a231c6
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fhdl: tristate support
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2013-02-15 00:17:24 +01:00 |
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Sebastien Bourdeauducq
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63d399b6ad
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fhdl/autofragment: from_attributes
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2013-02-11 18:34:01 +01:00 |
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Sebastien Bourdeauducq
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7ff61d8930
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doc: fix signal desc layout
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2013-02-10 19:39:18 +01:00 |
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Sebastien Bourdeauducq
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d78fc48805
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Merge branch 'master' of github.com:milkymist/migen
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2013-02-10 19:03:32 +01:00 |
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Sebastien Bourdeauducq
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1794b45ed3
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doc/dataflow: remove ActorNode
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2013-02-10 19:03:18 +01:00 |
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Sebastien Bourdeauducq
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f2665efbfe
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doc/dataflow: remove ALA
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2013-02-10 18:57:03 +01:00 |
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Sebastien Bourdeauducq
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b988003878
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doc: multiple clock domains
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2013-02-10 18:56:45 +01:00 |
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Sebastien Bourdeauducq
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6bca9c8b98
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doc: do not inline examples as this never works with most Sphinx setups ...
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2013-02-10 18:45:06 +01:00 |
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Sebastien Bourdeauducq
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3f063db281
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doc: update to new Migen APIs
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2013-02-10 18:42:47 +01:00 |
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Sebastien Bourdeauducq
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92b67df41c
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sim: default runner to Icarus Verilog
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2013-02-09 17:04:53 +01:00 |
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Sebastien Bourdeauducq
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bd6856ba7a
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flow/perftools: finish removing ActorNode
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2013-02-09 17:03:48 +01:00 |
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Sebastien Bourdeauducq
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473fd20f8c
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fhdl/structure: store clock domain name
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2013-01-24 13:49:49 +01:00 |
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Sebastien Bourdeauducq
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3201554f76
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fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
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2013-01-23 15:13:06 +01:00 |