Commit Graph

4376 Commits

Author SHA1 Message Date
Gabriel L. Somlo e90caa8683 tools/litex_sim: restore functionality of '--with-sdram' option
After LiteDRAM commit #50e1d478, an additional positional argument
('databits') is required by the PhySettings() constructor.

The value used here (32) will generate a 64MByte simulated SDRAM.
2019-05-23 08:56:50 -04:00
enjoy-digital 3a72688b28
Merge pull request #183 from xobs/usb-to-0x43
Use 0x43/0xc3 for USB bridge magic packet
2019-05-21 07:19:15 +02:00
Sean Cross 014c950580 remote: usb: print "access denied" error
When we get an error with errno 13, it means that the user doesn't
have access to the USB device.  Rather than silently eating this
error and returning -1, print out a message to aid in debugging.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-21 09:36:18 +08:00
Sean Cross faf6554c89 remote: usb: use 0x43/0xc3 for packet header
The previous value -- 0xc0 -- is used by Windows all the time to query
special descriptors.  This was causing a conflict when using the USB
bridge on a Windows device.

Change the magic packet from "Vendor: Device" queries to "Vendor:
Other" by setting the bottom two bits.

Signed-off-by: Sean Cross <sean@xobs.io>
2019-05-21 09:14:18 +08:00
Florent Kermarrec 10670e22ac soc/cores/minerva: update to latest 2019-05-17 22:21:57 +02:00
enjoy-digital a3134f13b1
Merge pull request #182 from gsomlo/gls-nexys4-eth-fixup
boards/nexys4ddr: ethernet support fix-up
2019-05-17 16:33:34 +02:00
Gabriel L. Somlo 5707bdc0a4 boards/nexys4ddr: ethernet support fix-up
Commit 5f6e7874 added ethernet support, let's now also expose it via
the "--with-ethernet" command line argument.
2019-05-17 10:06:12 -04:00
Florent Kermarrec 0a8699f1e6 Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-05-16 15:15:30 +02:00
Florent Kermarrec 526ba1b165 soc_core: remove csr_expose and add add_csr_master method
This could be useful in specific case were we don't have a wishbone master
but just want to have a csr bus and allow the user to define it.

/!\ Since there is no arbitration on between the CSR masters, use this with
precaution /!\
2019-05-16 15:14:55 +02:00
Florent Kermarrec 1ea22d49b7 software/include/base/csr-defs.h: add specific CSR_IRQ_MASK/PENDING for Minerva 2019-05-15 22:40:32 +02:00
Florent Kermarrec f25707012f software/bios/boot: remove specific linux commands (not needed with device tree) 2019-05-14 11:45:16 +02:00
Florent Kermarrec 938d00c283 boards/targets/de0nano: reduce to 50MHz sys_clk, simplify CRG 2019-05-14 11:45:12 +02:00
Florent Kermarrec 11838bae20 platforms/de0nano: change serial pins (put then next to the GND pin) 2019-05-14 11:45:06 +02:00
Florent Kermarrec eb6fa45833 cpu/vexriscv/core: update 2019-05-13 10:59:26 +02:00
Florent Kermarrec 0cad80e935 cpu/vexriscv: update submodule (new linux variant) 2019-05-13 10:59:03 +02:00
Florent Kermarrec 5f6e787494 boards/nexys4ddr: add ethernet support (RMII 100Mbps) 2019-05-13 10:18:23 +02:00
Florent Kermarrec 0ba1cb8756 boards/targets/netv2: +x 2019-05-11 12:39:02 +02:00
Florent Kermarrec 2f2b9b319f soc/cores: remove cordic
Cordic is useful for DSP cores but not as a Soc building block.
2019-05-11 09:36:53 +02:00
Florent Kermarrec 6e4ac1c493 LICENSE: clarify 2019-05-11 09:26:51 +02:00
Florent Kermarrec 67159349d6 soc/interconnect: remove axi_lite
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has  proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
2019-05-11 09:12:20 +02:00
Florent Kermarrec 745d83a332 boards: add initial NeTV2 support (clocks, leds, dram, ethernet) 2019-05-10 18:55:40 +02:00
Florent Kermarrec a49d170a6d soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy 2019-05-10 15:46:22 +02:00
Florent Kermarrec 7445b9e2e0 soc/integration/soc_core: allow user to defined internal csr/interrupts
For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.
2019-05-10 11:05:34 +02:00
Florent Kermarrec f333abcfcb boards/targets: use new add_csr method 2019-05-09 23:50:43 +02:00
Florent Kermarrec d76a2c7db2 tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method) 2019-05-09 23:33:08 +02:00
Florent Kermarrec b6be534cd6 soc/integration/soc_core: rework csr assignation/reservation
Similar refactor than on interrupts. Adds a add_csr method but still
retro-compatible with old way to declare CSRs.
2019-05-09 23:32:22 +02:00
Florent Kermarrec 3f09af6d6e boards/targets: declare ethmac interrupt with new add_interrupt method
The previous way to define interrupt is still valid, but using add_interrupt
method will ease maintenance
2019-05-09 12:13:15 +02:00
Florent Kermarrec 2abb3e809c Merge branch 'master' of http://github.com/enjoy-digital/litex 2019-05-09 11:57:19 +02:00
Florent Kermarrec 47dc87584f integration/soc_core: rework interrupt assignation/reservation
The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.

Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
2019-05-09 11:54:22 +02:00
Florent Kermarrec 3ee9ce0529 test/test_targets: fix test_ulx3s name 2019-05-09 11:48:57 +02:00
Florent Kermarrec 435cdad083 boards/targets: fix ulx3s/versa_ecp5 build 2019-05-09 11:48:32 +02:00
Mateusz Holenko 8caa38bc25 cpu: add `reserved_interrupts` property 2019-05-09 09:00:06 +02:00
enjoy-digital c11eb4b51c
Merge pull request #179 from gsomlo/gls-xtra-addrlen
soc/integration/cpu_interface: more arch-specific address size fixes
2019-05-09 08:57:31 +02:00
Gabriel L. Somlo c264a00964 soc/integration/cpu_interface: more arch-specific address size fixes
When generating arch-specific include files (generated/[mem|csr].h)
ensure address literal defines are suffixed by 'L', denoting their
'unsigned long' type. This inhibits compiler warnings when values
computed based on these constants are cast to pointers.

Also ensure csr_[read|write][b|w|l]() function declarations have
'unsigned long' address arguments.

Finally, restore the correct (32-bit, (unsigned *)) expected
behavior of the MMPTR() macro, inadvertently converted to an
arch-specific sized access (unsigned long *) by commit 5c2b8685.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-05-08 16:03:36 -04:00
Florent Kermarrec ff5179153c boards/targets: make sys_clk_freq a parameter
Most of the targets can now generate an abritrary sys_clk_freq from onboard XO.
2019-05-07 18:44:03 +02:00
Florent Kermarrec a8cbe4ad84 boards/targets/minispartan6: for now revert experimental s6pll clocking 2019-05-07 13:05:28 +02:00
Florent Kermarrec 6fcbf10eb9 boards/plarforms/minispartan6: default to xc6slx25 2019-05-07 12:48:36 +02:00
Florent Kermarrec b7e3713388 bios/boot/ update linux memory mapping 2019-05-07 11:59:28 +02:00
Florent Kermarrec 190ff89aaa tools/litex_term: add json support to load images to memory, allow passing speed as float
example json file (serialboot.json):
{
	"binaries/Image":         "0xc0000000",
	"binaries/rootfs.cpio":   "0xc2000000",
	"binaries/rv32.dtb":      "0xc3000000",
	"emulator/emulator.bin":  "0x20000000"
}

example command:
lxterm --images=serialboot.json /dev/ttyUSBX
2019-05-06 23:56:33 +02:00
enjoy-digital a50aff2c74
Merge pull request #178 from daveshah1/vexriscv_linux_yosys
vexriscv: Fix some floating signals
2019-05-04 20:02:42 +02:00
David Shah a048ba47c4 vexriscv: Fix some floating signals
Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:27:21 +01:00
Florent Kermarrec fcd518b5d0 bios/boot: add specific flash_boot for linux with vexriscv 2019-05-04 11:27:01 +02:00
Florent Kermarrec 1ba1ad9a00 bios/boot: rename MM_RAM to EMULATOR_RAM 2019-05-03 19:47:36 +02:00
Florent Kermarrec fbb24720f0 soc/get_mem_data: add direct support for regions
We now support passing filename (offset=0), json file and regions
2019-05-03 13:24:06 +02:00
Florent Kermarrec 0714816f31 soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone 2019-05-03 11:59:06 +02:00
Florent Kermarrec c6d0d23445 soc/interconnect/axi: add AXI Lite definition 2019-05-03 09:43:12 +02:00
Florent Kermarrec 9fab4752c4 soc/interconnect/axi: add comment on axi signas that are present but not used 2019-05-03 09:30:59 +02:00
Florent Kermarrec 5989076346 cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant 2019-05-03 09:30:26 +02:00
Florent Kermarrec 21bf10383d bios/boot: add liftoff banner just before booting 2019-05-02 18:26:35 +02:00
Florent Kermarrec 8f4685b3b1 bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config 2019-05-02 16:34:41 +02:00