Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,376 Commits 37 Branches 13 Tags 47 MiB
Commit Graph

4376 Commits

Author SHA1 Message Date
Florent Kermarrec d2ad14417a targets/ac701: cleanup and make it similar to others targets. 
Still supports EthernetSoC with RGMII and 1000BaseX.
 2019-04-23 11:10:35 +02:00
Florent Kermarrec a24bf72fc7 targets/xilinx: remove keep attribute on clock going to idelayctrl 
Causes P&R issues with Vivado.
 2019-04-23 10:51:36 +02:00
Florent Kermarrec ea8dbff86e boards/platform/ac701: add proper copyright, cleanup to be similar to others platforms 2019-04-23 10:50:19 +02:00
Florent Kermarrec 0122982e09 boards/platforms/kc705: provide only one default programmer as others platforms 2019-04-23 10:00:52 +02:00
Vamsi K Vytla 89a590263f boards: Xilinx ac701 dev board support 2019-04-23 09:48:16 +02:00
Michael Betz 88b882c7e0 build/xilinx/ise.py: write .v file for post synthesis sim 2019-04-23 09:22:48 +02:00
Florent Kermarrec 7396ebbb38 build/xilinx/programmer: cleanup XC3SProg position parameter 2019-04-23 09:20:59 +02:00
Michael Betz f579cbc603 build/xilinx/programmer: add position parameter to XC3SProg 2019-04-23 09:16:42 +02:00
Vamsi K Vytla fb4f881857 .gitignore: ignore tilde files 2019-04-23 09:10:11 +02:00
Florent Kermarrec 535d86727a targets/minispartan6: use S6PLL in CRG 2019-04-23 06:44:29 +02:00
Florent Kermarrec 40342404f2 cores/clock: add divclk_divide_range on S6PLL/S6DCM 2019-04-23 06:43:48 +02:00
Florent Kermarrec 0d282f38f9 cores/clock: use common XilinxClocking class for all Xilinx clocking modules 2019-04-23 06:35:39 +02:00
Michael Betz 83699ea0a5 cores/clock: add initial Spartan6 PLL/DCM support 2019-04-23 06:23:00 +02:00
Florent Kermarrec eff141da2d build: add git version (sha-1) used to create the scripts 2019-04-23 06:03:12 +02:00
Florent Kermarrec cc141a64b9 build: scripts are generated by LiteX 2019-04-23 05:38:33 +02:00
Florent Kermarrec 115c842ef0 build/xilinx/vivado: cleanup pull request #170 2019-04-23 05:33:56 +02:00
enjoy-digital 3b24b8d5b4
Merge pull request #170 from ldoolitt/master 
build/xilinx/vivado: only try Xilinx setup if vivado is not already i…
 2019-04-23 05:26:54 +02:00
Larry Doolittle fda18fd6ef build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path 
Only affects the non-Windows code path.
Uses python distutils, already used elsewhere.
 2019-04-22 15:42:31 -07:00
Florent Kermarrec 7d278854d5 global: switch to VexRiscv as the default CPU 
VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
 2019-04-22 09:41:07 +02:00
Florent Kermarrec 28d80bd641 ci: fix test_targets/test_simple 2019-04-22 08:53:43 +02:00
Florent Kermarrec b7f53fb93c test: remove waveforms generation 2019-04-22 08:41:28 +02:00
Florent Kermarrec e98ac680c1 travis: simplify, enable and add RISC-V toolchain to build targets 2019-04-22 08:32:00 +02:00
Florent Kermarrec 8c78997089 boards/platforms: add separators, cleanup imports 2019-04-21 00:44:23 +02:00
Florent Kermarrec cb8c26d1b8 boards/platforms: provide only one default programmer per platform. 
create_programmer is not really longer used, so try to keep it simple.
 2019-04-21 00:17:03 +02:00
Florent Kermarrec e1d202df02 boards/platforms/kc705: only keep Vivado support 
There is no reason still using ISE on 7-Series.
 2019-04-21 00:04:56 +02:00
Florent Kermarrec 53c7be6e46 boards: always define timing constraints the same way (1e9/freq_mhz) 2019-04-20 23:56:27 +02:00
Florent Kermarrec 02ffbed5e3 boards/targets/ulx3s: allow running test_targets on it 2019-04-20 23:47:05 +02:00
Florent Kermarrec 5a1925df2e boards/targets: add keep attribute directly in crg 
This makes it systematic and avoid having to add it later.
 2019-04-20 23:43:44 +02:00
enjoy-digital 67a79d7c92
Merge pull request #167 from xobs/network-flag-check 
litex_server: check socket flags exist before using them
 2019-04-20 12:23:24 +02:00
Sean Cross f71b8d4f57 litex_server: check socket flags exist before using them 
Some flags are only available on certain platforms.  Verify these flags
exist prior to using them when opening a socket.

See
https://stackoverflow.com/questions/14388706/socket-options-so-reuseaddr-and-so-reuseport-how-do-they-differ-do-they-mean-t
for more information

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-20 17:28:26 +08:00
Florent Kermarrec 9ee6c35b42 tools: move from litex.soc.tools to litex.tools and fix usb.core import 2019-04-20 10:44:53 +02:00
enjoy-digital 49fd93ae83
Merge pull request #165 from xobs/vexriscv-cpu-reset-address 
Vexriscv cpu reset address
 2019-04-19 19:16:16 +02:00
enjoy-digital ca6065a6a1
Merge pull request #164 from xobs/litex-usb-server 
Litex usb server support
 2019-04-19 19:14:15 +02:00
Sean Cross c69183648f utils: litex_server: add usb support 
Add `--usb` and associated arguments to create a litex bridge over
USB.  This makes use of the new CommUSB module.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 18:02:42 +01:00
Sean Cross 9dd59d6301 tools: remote: add usb communications protocol 
This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 17:29:50 +01:00
Florent Kermarrec 9cbed91b3e soc/interconnect/axi: add AXIBurst2Beat 
Converts AXI bursts commands to AXI beats.
 2019-04-19 12:13:16 +02:00
Florent Kermarrec 5a8115d9e1 soc/interconnect/avalon: add description 2019-04-19 11:43:15 +02:00
Sean Cross c780fb22b7 Merge branch 'master' of https://github.com/enjoy-digital/litex 2019-04-19 16:47:55 +08:00
Florent Kermarrec fa95608694 soc/integration/soc_zynq: fix HP0 connections 2019-04-19 10:21:56 +02:00
Florent Kermarrec a78ca2de92 build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog) 2019-04-19 09:18:25 +02:00
Sean Cross e2cf45b8a9 cpu: vexriscv: allow cpu_reset_address to be overridden 
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal.  That way the reset address can be modified after
synthesis, in dual-core or debug situations.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-04-19 13:04:57 +08:00
Florent Kermarrec a92e90b215 soc/interconnect: add avalon with converters to/from native streams 2019-04-18 18:42:29 +02:00
enjoy-digital d860eeea4f
Merge pull request #162 from antmicro/full-conf-vexriscv 
Add full and full_debug CPU variant of VexRiscv
 2019-04-17 19:01:55 +02:00
enjoy-digital ce81a39ce9
Merge pull request #163 from gsomlo/gls-verilated-cmdargs 
build/sim/core: Initialize Verilator commandArgs
 2019-04-17 18:59:28 +02:00
Gabriel L. Somlo e1683078ec build/sim/core: Initialize Verilator commandArgs 
Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".
 2019-04-17 10:39:35 -04:00
Joanna Brozek 40de01bcb0 vexriscv: Add full and full_debug CPU variant 2019-04-17 09:09:35 +02:00
Florent Kermarrec 017147c623 build/altera: switch to sdc constraints, add add_false_path_constraints method 2019-04-16 16:57:23 +02:00
Florent Kermarrec 1275e2f150 build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints 
MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.
 2019-04-15 16:48:47 +02:00
Florent Kermarrec c252972bef soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale 2019-04-15 11:36:42 +02:00
Florent Kermarrec f986974d60 soc/cores/clock: improve presentation 2019-04-15 10:57:00 +02:00