Commit Graph

15 Commits

Author SHA1 Message Date
Florent Kermarrec 1d4dc45436 LiteXXX cores: use format in prints 2015-03-03 10:29:28 +01:00
Florent Kermarrec f27e7a4b22 litesata: remove unneeded clock constraint 2015-03-03 10:24:05 +01:00
Sebastien Bourdeauducq ff29c86fe1 litesata/kc705: use FMC pin names 2015-03-03 01:02:50 +00:00
Florent Kermarrec 649cdeb265 liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen 2015-03-01 16:48:41 +01:00
Florent Kermarrec 9e01bf5fdd litesata: create example design derived from SoC 2015-03-01 11:33:38 +01:00
Florent Kermarrec c21a7956c8 liteXXX cores: remove Identifier duplication 2015-03-01 11:24:58 +01:00
Florent Kermarrec 67ca0da1d9 liteXXX cores: share same methodology for on-board tests 2015-03-01 11:21:12 +01:00
Florent Kermarrec 7b464b2b1c litesata: create specialized kc705 platform to avoid duplicating things already in mibuild 2015-03-01 11:03:15 +01:00
Florent Kermarrec b34be816ec liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH) 2015-02-28 22:23:48 +01:00
Florent Kermarrec 0fd1b9df8d liteXXX cores: remove redefinition of get_csr_csv 2015-02-28 21:45:05 +01:00
Florent Kermarrec 5bd1ab7fa1 liteXXX cores: update README and doc 2015-02-28 21:40:59 +01:00
Florent Kermarrec 69e869893d remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) 2015-02-28 11:36:15 +01:00
Florent Kermarrec 8e67d6e69f liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates) 2015-02-28 11:08:17 +01:00
Florent Kermarrec 0dfca49e68 litesata: move file and modify import to misoclib.mem.litesata 2015-02-28 11:03:24 +01:00
Florent Kermarrec b6358be0a1 merge litesata 2015-02-28 10:48:08 +01:00