74467e3b38
test/test_axi/test_axi_width_converter: Switch to DUT_ref (To avoid breaking CI).
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We'll switch back to DUT when AXI Converter will be fixed.
2022-07-25 12:34:38 +02:00
982f94ba8d
test: add axi 64b to 32b conversion test
2022-07-25 00:20:48 +02:00
65d5161408
test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width
2022-07-20 02:44:57 +02:00
bffd59726c
test/axi_lite: rename a test for clarity; parametrize address and data width; add another test call with 64b data width
2022-07-20 02:43:43 +02:00
9c3663f3d2
test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:15:48 +02:00
ec9d1c4fd0
CI: Disable more CPUs.
2022-06-27 22:43:01 +02:00
f898423390
test/test_cpu: Diable mor1kx/picorv32 for now due to issue with newer Verilator.
2022-06-27 19:54:50 +02:00
cbd873a33e
test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
3f8cafeb58
test/test_cpu: Disable cva5 and enable marocchino/mor1kx.
2022-06-03 17:14:52 +02:00
c0fc342823
test/test_cpu: Simplify using subTest/lists, test more RISC-V CPUs and comments for untested CPUs.
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Also use --opt-level=O0 to reduce compilation time (execution is a bit slower but since we are only
executing the BIOS here, total test time is still reduced).
2022-06-03 16:16:21 +02:00
69451fad09
test/test_cpu: Disable test_cva6 for now since seems to be failing.
2022-05-25 09:32:30 +02:00
c95ddbbff8
UART_POLLING
2022-05-19 15:07:46 +02:00
22abe1d543
Add tests for FIFOSyncMacro
2022-04-27 10:53:52 +02:00
8c1bc139ab
soc/interconnect/wishbone: Cleanup in burst cycles support logic
2022-04-12 15:32:29 +02:00
ad46a57403
test/test_wishbone: Add test for Wishbone SRAM constant address burst cycle
2022-04-12 14:06:22 +02:00
cdd216f692
test/test_wishbone: Add basic test for SRAM with burst cycles support
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Tests incrementing address burst cycle with linear and wrapped increments.
Only 4-beat wrap burst is tested in `test_sram_burst_wrap` test.
2022-04-12 14:06:22 +02:00
ed6a6a83a9
litex_setup: Switch to manual install for Amaranth/Minerva (No longer supporting Python 3.6).
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We could revert when upgrading LiteX python requirement.
2022-04-04 15:39:05 +02:00
d39c3ed626
soc/cores/led: Review/Rework #1265 .
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- Split FSM in Main FSM/Xfer FSM to decouple Led data read from bit xfer and do read during xfer.
- Only keep optimization that are easily to understand.
- Default to new WS2812 revision (Since also works on old revision).
- Test 75/50/25MHz sys_clk_freq.
2022-04-04 15:24:54 +02:00
67369403a9
Improve WS2812 timings and add different hardware revision support
2022-04-03 17:09:56 +02:00
6ef96b17bc
soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).
2022-03-21 15:21:08 +01:00
dbde036162
soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.
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The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
2022-03-01 09:11:55 +01:00
f62eca77e3
test/test_axi: Minor cleanups.
2022-02-17 15:13:05 +01:00
77c6cdd78e
cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.
2022-01-25 11:09:15 +01:00
ea6bb3dd80
test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore.
2022-01-25 10:49:33 +01:00
e50ff33c6e
test/test_cpu: Disable Minerva test for now.
2021-12-13 16:51:23 +01:00
12d53790a9
test/test_cpu: Prepare microwatt/lm32 test.
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microwatt: Still requires Yoys/GHDL-Synth installation.
lm32: Still requires prebuilt toolchain.
2021-10-26 16:37:38 +02:00
e617f52e34
test/test_cpu: Comment test_mor1kx for now (test work but issue seems related to the pre-built toolchain).
2021-10-26 16:30:02 +02:00
cb9f0fb1b0
ci/test_cpu: Install OpenRISC GCC toolchain in CI and add mor1kx to test_cpu.
2021-10-26 15:45:43 +02:00
71a91eac15
test: Rename test_boot.py to test_cpu.py.
2021-10-26 08:35:16 +02:00
47b3c9bc08
soc/interconnect/packet: Remove last_be support in LiteX, specialized Packetizer/Depacketizer have been moved to LiteEth to simplify development and avoid eventual regresion on others cores.
...
As seen during the last LiteEth developments, last_be data qualifier is not easy to handle correctly and should be replaced by a simpler data qualifier (similar to AXI's tkeep/tstrb). It will
be easier to do so by having a local copy of Packetizer/Depacketizer directly in LiteEth (still with last_be support) and work on the simpler data qualifier in LiteX (and test it on LitePCIe).
2021-10-25 11:17:36 +02:00
2886fe1701
Add bios test mode for CI ( #1076 )
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* Add bios test mode for CI
This enables to test the booting of each CPU configurations with the bios in Verilator simulation.
2021-10-24 12:08:58 +02:00
8e448592f0
interconnect/packet: Revert old last/ready logic handling (new one breaks test_packet) and comment out test_packet2 tests (does not seems to be working with previous last/ready handling).
2021-10-23 18:21:47 +02:00
59fd2d31c7
test/test_packet2: Fix imports.
2021-10-23 17:54:00 +02:00
32bb2554bc
test: Rename new test_packet/stream to test_packet2/stream2 and revert old tests.
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Old and new tests are complementary and would need to be merged.
2021-10-23 17:40:41 +02:00
434b3a3654
Merge pull request #1008 from lschuermann/dev/packetizer-last_be-fix
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{Dep,P}acketizer: properly handle last_be wraparound
2021-10-23 17:33:29 +02:00
99f3498f2d
cores/icap/ICAP: Add Register read capability.
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Useful to get some internal status, ex the IDCode or know if the executed bistream
in a multiboot configuration is the operational or fallback one.
2021-10-04 17:22:57 +02:00
3504904c09
cores/icap/ICAP: Rewrite using with an FSM instead of Timeline (will be easier to extend).
2021-10-04 15:06:03 +02:00
9416e30249
test/test_icap: Add IPROG sequence check.
2021-10-04 14:41:38 +02:00
cb2f2d7021
cores/icap/ICAP: Rewrite using constants and cleanup.
2021-10-04 14:25:40 +02:00
6733a3e3e6
clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search
2021-09-15 00:07:43 -05:00
a568b7e26a
test_packet.py: test randomly generated headers
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Also includes some fixes for the non-last_be test path such that the
expected behavior is the one currently oberserved with the Packetizer
and Depacketizer.
2021-09-10 15:30:05 +02:00
958bcaad2e
test_packet.py: add last_be tests
2021-09-10 12:30:04 +02:00
037294dc3b
test_packet.py: support passing debug_print parameter
2021-09-09 16:37:26 +02:00
6bda383178
test_packet.py: support {Dep,P}acketizer behavior without last_be
2021-09-09 16:37:26 +02:00
a08271b83a
test_packet.py: utilize generic stream_inserter/colletor interface
2021-09-09 16:08:12 +02:00
ca50cba986
Rewrite test_stream.py with reusable stream_inserter/collector
2021-09-09 16:08:12 +02:00
79ac09316a
interconnect/axi/AXIBurst2Beat: Fix BURST_WRAP case.
2021-08-06 16:41:58 +02:00
1ce48a973b
clock/lattice_ecp5: Fix and rework 4-output solver implementation.
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The implementation was causing regressions on actual designs, rework done:
- Only keep a common iteration loop as before.
- Add iteration on CLKO dividers (to fall in the VCO range).
- Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it.
- If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
2021-07-26 14:00:00 +02:00
8954041a93
clock/lattice_ecp5/ECP5PLL: Only consider non-dpa clocks as feedback
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Dynamically adjusting the phase of a feedback will cause it to unlock.
The phase adjust ports are shared by all the outputs, so there is no
technical way to prevent this. Allow the user to indicate that they
will not adjust a clock when requesting an output by setting
uses_dpa=False, and only consider those that the user has promised not
to use.
2021-07-08 08:14:14 -05:00
f6b2135cc9
test/test_timer: Update.
2021-05-27 19:37:51 +02:00
Florent Kermarrec
Ilia Sergachev
Robert Szczepanski
Massimiliano Giacometti
Rafal Kolucki
Wolfgang Nagele
Navaneeth Bhardwaj
George Hilliard
Leon Schuermann