c4e635ea5c
Merge pull request #1393 from trabucayre/fix_vivado_yosys_synth
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build/xilinx/vivado: Insert the yosys call into script_content only when synth_mode == yosys
2022-08-05 17:30:14 +02:00
b792bfd8b2
tools/litex_client/run_gui: Add Identifier/Leds/Buttons peripherals support.
2022-08-05 15:25:13 +02:00
ae44b70833
build/xilinx/vivado: Insert the yosys call into script_content only when synth_mode == yosys
2022-08-05 14:51:39 +02:00
95a4814184
tools/litex_client: Improve run_gui termination.
2022-08-05 14:12:37 +02:00
68006a2144
tools/litex_client: Add XADC (7-Series) suppport to GUI.
2022-08-05 13:49:26 +02:00
ae8deda186
interconnect/axi/AXIArbiter: valid also needs to be filtered.
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Fixes un-sollicited valids on masters.
2022-08-05 11:20:52 +02:00
a286d77e01
build/xilinx/vivado: Switch from .format to f-strings.
2022-08-05 08:59:32 +02:00
2fba07daf8
build/gowin: Use build_name instead of top for generated files.
2022-08-05 08:30:34 +02:00
3c1e8e74fc
build: Cosmetic cleanups.
2022-08-05 08:22:36 +02:00
c2b62a6b0c
Merge pull request #1392 from tpwrules/fix-vexriscsmp-quartus
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cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus
2022-08-05 08:02:29 +02:00
1f2d0e120b
Merge pull request #1391 from dlobato/fix-verilator-fst-trace
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build/sim/verilator: fixed missing placeholder
2022-08-05 08:02:08 +02:00
195cc915ed
cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus
2022-08-04 21:34:56 -05:00
41e1ccce4b
build/sim/verilator: fixed missing placeholder
2022-08-04 20:03:29 +01:00
926fb9a30a
build/xilinx/vivado: Fix build.
2022-08-04 17:59:12 +02:00
47df2f6983
bios/cmd_bios: Add buttons command to get buttons value.
2022-08-04 16:31:12 +02:00
8250f56f80
Merge pull request #1389 from trabucayre/rfc_yosys_nextpnr_wrapper
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RFC: yosys nextpnr wrapper
2022-08-04 15:02:35 +02:00
1ce378e24d
Merge pull request #1390 from tpwrules/add-linux-vexriscv_smp
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cores/cpu/vexriscv_smp: add default cores used by linux with l2 cache
2022-08-04 12:19:37 +02:00
6932fc51e2
Merge pull request #1388 from p-woj/json2renode-fb-plic
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tools/litex_json2renode: Add video_framebuffer support, vexriscv interrupt fixes
2022-08-02 15:35:06 +02:00
35e0de043d
cores/cpu/vexriscv_smp: add default cores used by linux with l2 cache
2022-07-31 22:31:33 -05:00
7789e1875a
build/gowin: Fix build regression (build_name -> self._build_name).
2022-07-26 09:59:20 +02:00
d5b0f9263d
build: lattice/radiant.py xilinx/common.py xilinx/ise.py xilinx/vivado.py: use yosys_wrapper
2022-07-25 22:35:55 +02:00
21105669a8
build: lattice/icestorm, lattice/oxide, lattice/trellis, xilinx/yosys_nextpnr: inherits from YosysNextPNRToolchain
2022-07-25 22:05:21 +02:00
6d6076d8c6
build/yosys_nextpnr_toolchain: GenericToolchain subclass targeted for toolchains based on Yosys+nextPNR+packer tool suite
2022-07-25 22:00:26 +02:00
32c750c12e
build/nextpnr_wrapper: a NextPNR wrapper
2022-07-25 21:58:44 +02:00
b2adabbece
build/yosys_wrapper: a Yosys wrapper
2022-07-25 21:58:18 +02:00
456822a5fa
tools/litex_json2renode: Add video_framebuffer support
2022-07-25 13:38:12 +02:00
c149f3e4dd
tools/litex_json2renode: Add find_memory_region helper
2022-07-25 13:38:12 +02:00
98168492de
tools/litex_json2renode: Save filtered memory regions for peripheral generators
2022-07-25 13:38:12 +02:00
124a2b2d56
tools/litex_json2renode: Don't disable built-in IRQ controller on vexriscv_smp
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The built-in IRQ controller is needed by linux-on-litex-vexriscv
2022-07-25 13:37:25 +02:00
dae22a0d9d
tools/litex_json2renode: Update PLIC interrupt configuration
2022-07-25 13:30:09 +02:00
212db12b1d
tools/litex_json2renode: Skip braces on MappedMemory registration
2022-07-25 13:25:17 +02:00
4f471490a8
tools/litex_json2renode: Output silenced range start address as hex
2022-07-25 13:25:17 +02:00
74467e3b38
test/test_axi/test_axi_width_converter: Switch to DUT_ref (To avoid breaking CI).
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We'll switch back to DUT when AXI Converter will be fixed.
2022-07-25 12:34:38 +02:00
c734732ece
Merge pull request #1386 from sergachev/feature/test_axi_width_conversion
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test: add axi 64b to 32b conversion test
2022-07-25 12:29:42 +02:00
f691aecb95
Merge pull request #1387 from sergachev/fix/cva6
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cpu/cva6: add optional peripheral bus conversion +
2022-07-25 12:22:29 +02:00
8de83550a1
Merge pull request #1385 from sergachev/fix/verilator_includes
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sim: enable relative include paths for verilator
2022-07-25 12:11:04 +02:00
29c2aed64a
Merge pull request #1384 from trabucayre/fix_xilinx_yosys_nextpnr_toolchain
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build/xilinx/yosys_nextpnr: _run_make -> run_script
2022-07-25 12:10:41 +02:00
982f94ba8d
test: add axi 64b to 32b conversion test
2022-07-25 00:20:48 +02:00
20affcfc31
cpu/cva6: add optional peripheral bus conversion to bypass axi width conversion problem; fix add_jtag; cleanup
2022-07-24 23:41:49 +02:00
7613c90fcd
sim: enable relative include paths for verilator
2022-07-24 23:02:41 +02:00
f37a505c46
build/xilinx/yosys_nextpnr: _run_make -> run_script
2022-07-23 15:21:50 +02:00
b9a1fec30f
soc/software: Allow enabling LTO through lto/--lto paramter/argument.
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LTO has been removed by default since causing issues with some CPUs/Toolchains.
For configuration that work corretly, it's still interesting to be able to use it,
this commit allow it through lto/--lto parameter/argument.
2022-07-21 13:15:44 +02:00
e3a536ab5f
soc/SoCBusHandler: Add get_address_width method to get address_width depending bus standard.
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This fixes SDCard/SATA build with and AXI/AXI-Lite Bus.
2022-07-21 12:50:45 +02:00
7acb6d468d
Merge pull request #1380 from antmicro/rkol/f4pga-generictoolchain
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build/xilinx: Fix F4PGA building flow
2022-07-20 14:12:58 +02:00
7a4af24706
Merge pull request #1381 from sergachev/feature/sim_compiler_job_limit
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sim/verilator: add an option to limit the number of compiler jobs
2022-07-20 14:12:23 +02:00
bc62b5ad9f
sim/verilator: add an option to limit the number of compiler jobs
2022-07-20 12:20:25 +02:00
57f8b6810d
build/xilinx: Fix F4PGA building flow
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Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
2022-07-20 10:35:45 +02:00
66015a346e
Merge pull request #1379 from sergachev/axi_tests
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Improve AXI Lite tests
2022-07-20 08:02:31 +02:00
bdf5f19885
Merge pull request #1378 from sergachev/fix/openc906
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cpu/openc906: fix bus name
2022-07-20 08:01:27 +02:00
65d5161408
test/axi_lite: parametrize address and data width in another test; add another test call with 64b data width
2022-07-20 02:44:57 +02:00
enjoy-digital
Gwenhael Goavec-Merou
Thomas Watson
David Lobato
Dolu1990
Mateusz Hołenko
Piotr Wojnarowski
Ilia Sergachev
Rafal Kolucki