Commit Graph

3281 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq f4c5197047 travis: workaround for conda noarch bug 2015-10-21 16:17:40 +03:00
whitequark 5e65938fde conda: build migen as noarch. 2015-10-21 13:30:08 +03:00
whitequark 70a86a3282 conda: include hash in commit. 2015-10-21 13:30:08 +03:00
Sebastien Bourdeauducq 2bbcc218f3 sim: fix case break 2015-10-20 17:18:33 +08:00
Sebastien Bourdeauducq 60ae9dce0d sim: do not use py35 collections.Generator 2015-10-20 16:37:54 +08:00
Sebastien Bourdeauducq 02e2366015 travis: workaround for conda noarch bug 2015-10-19 23:02:37 +08:00
Sebastien Bourdeauducq 5d75eb5e6a conda: noarch 2015-10-19 22:54:30 +08:00
Sebastien Bourdeauducq ac5271e80e sim: truncate case test value 2015-10-19 20:08:46 +08:00
Sebastien Bourdeauducq ee283575d8 test: fix divider testbench 2015-10-19 19:41:18 +08:00
Sebastien Bourdeauducq 1f89900b16 sim: generators are also iterables... 2015-10-19 19:21:20 +08:00
Sebastien Bourdeauducq 02d804feab sim: accept iterables as generator list 2015-10-19 19:18:17 +08:00
Sebastien Bourdeauducq 0999a17319 verilog, sim: accept iterables in FHDL statements 2015-10-19 19:17:26 +08:00
Sebastien Bourdeauducq 4d9b2fff63 genlib/fsm: fix return value of _get_register_control 2015-10-19 19:03:43 +08:00
Sebastien Bourdeauducq 766b0bee65 MANIFEST.in: fix lm32 data directory 2015-10-19 16:30:41 +08:00
Sebastien Bourdeauducq a824046bbc Revert "sim/core: fix Cat bitshift"
This reverts commit 6d6f91a02b.
2015-10-19 16:08:42 +08:00
Sebastien Bourdeauducq 6d6f91a02b sim/core: fix Cat bitshift 2015-10-19 16:07:45 +08:00
Sebastien Bourdeauducq 28962ff438 sim/core: truncate evaluated values before test in If 2015-10-19 15:58:21 +08:00
Sebastien Bourdeauducq e6452166c2 software: do not build libdyld and libunwind for lm32. Closes #22 2015-10-19 11:33:21 +08:00
Sebastien Bourdeauducq ec80f0fa7e build/vivado: quote paths in Tcl (prevents problems with \ on Windows) 2015-10-19 09:40:44 +08:00
Sebastien Bourdeauducq 4acb7bc662 sim: support execution of nested statement lists (typo) 2015-10-15 13:53:04 +08:00
Sebastien Bourdeauducq 3b7f1264f1 sim: support execution of nested statement lists 2015-10-15 13:52:24 +08:00
Sebastien Bourdeauducq 884faedc00 integration/builder: escape backslash in makefile defines 2015-10-14 21:45:36 +08:00
Sebastien Bourdeauducq 48d22a7588 genlib/fifo: width_or_layout -> width 2015-10-14 21:36:44 +08:00
Sebastien Bourdeauducq 93a615ade4 Merge branch 'new' of github.com:m-labs/misoc into new 2015-10-14 11:11:06 +08:00
Sebastien Bourdeauducq ecc4c573eb integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled
Reported by Florent Kermarrec
2015-10-14 11:09:53 +08:00
Florent Kermarrec f7787c3c13 software/bios: move romboot after serialboot and netboot
On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
2015-10-13 18:13:00 +02:00
Florent Kermarrec 9041868291 software/bios: move romboot after serialboot and netboot
On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
2015-10-13 17:49:29 +02:00
Sebastien Bourdeauducq 8817716d5f test/divider: subtests 2015-10-13 18:39:41 +08:00
Yann Sionneau b8283ec92c vivado progammer: allow to specify flash chip 2015-10-12 20:07:01 +02:00
Sebastien Bourdeauducq e0899c1424 sim: make sure replaced memory signals are always in VCD signal set 2015-10-05 12:24:32 +08:00
Sebastien Bourdeauducq e96eba4493 setup: include software and Verilog files
Broken on Python 3.5
error: can't copy 'misoc/software': doesn't exist or not a regular file
2015-10-05 12:08:02 +08:00
Florent Kermarrec c38d8175b7 interconnect/stream: add missing part of Demultiplexer 2015-10-05 00:10:55 +02:00
Sebastien Bourdeauducq af3723db14 setup: add entry points 2015-10-05 00:45:02 +08:00
Sebastien Bourdeauducq 5e8c4cc364 setup: fix readme 2015-10-05 00:44:50 +08:00
Sebastien Bourdeauducq 70e3280579 travis/conda: build for python 3.5 2015-10-05 00:25:25 +08:00
Sebastien Bourdeauducq 09bef1a016 travis/conda: build for python 3.5 2015-10-05 00:10:04 +08:00
Sebastien Bourdeauducq b1f8aa2a67 travis: activate py35 2015-10-04 23:12:07 +08:00
Sebastien Bourdeauducq d983782bed travis: activate py35 2015-10-04 23:11:16 +08:00
Sebastien Bourdeauducq 6258257573 travis: python 3.5 2015-10-04 23:08:29 +08:00
Sebastien Bourdeauducq 4ccb489036 travis: python 3.5 2015-10-04 23:08:14 +08:00
Sebastien Bourdeauducq 9c905830dc sdram: cleanup 2015-10-02 11:37:22 +08:00
Sebastien Bourdeauducq d21358fc26 liteeth_mini: fix imports, replace Counter and FlipFlop 2015-09-30 20:17:52 +08:00
Sebastien Bourdeauducq 617c6ecb47 interconnect/stream: add multiplexer and demultiplexer 2015-09-30 19:43:51 +08:00
Sebastien Bourdeauducq 6c01f80fc5 genlib/fifo: add missing imports 2015-09-30 18:58:46 +08:00
Sebastien Bourdeauducq 0c1e1c9769 test/fifo: do not use Record 2015-09-30 17:06:31 +08:00
Sebastien Bourdeauducq b3d5d1628c interconnect/stream: remove param, do not depend on FIFO Record support 2015-09-30 16:40:34 +08:00
Sebastien Bourdeauducq 1b8f313d40 lasmicon: do not depend on FIFO Record support 2015-09-30 16:40:04 +08:00
Sebastien Bourdeauducq 4451bb20e5 genlib/fifo: remove Record support 2015-09-30 16:39:33 +08:00
Sebastien Bourdeauducq c36029fa61 command line options support, CSR CSV, all targets building 2015-09-29 18:14:54 +08:00
Sebastien Bourdeauducq e1927b7cbb flterm: cleanup 2015-09-29 18:14:19 +08:00