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Author SHA1 Message Date
Florent Kermarrec
78b4f313bf mibuild/platforms/minispartan6: add device parameter (board can be populated with lx9 or lx25) 2015-03-21 18:28:09 +01:00
Florent Kermarrec
1a03c340c9 mibuild/platforms: review and fix small mistakes 2015-03-21 18:23:35 +01:00
Florent Kermarrec
3a38626556 mibuild/platforms: add minispartan6 (from Matt O'Gorman) 2015-03-21 18:22:26 +01:00
Florent Kermarrec
711540e15c targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics 2015-03-21 18:10:56 +01:00
Florent Kermarrec
1c0e306176 targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics 2015-03-21 18:07:10 +01:00
Florent Kermarrec
854058a8db sdram/module: add description and TODO list 2015-03-21 17:44:04 +01:00
Florent Kermarrec
52924ee1f2 sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705 2015-03-21 17:25:36 +01:00
Florent Kermarrec
fd2f8d4bb4 sdram: define MT46V32M16 and use it on m1/mixxeo 2015-03-21 17:04:58 +01:00
Florent Kermarrec
de2f1c31d5 sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
Florent Kermarrec
6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
 2015-03-21 12:55:39 +01:00
Robert Jordens
14b1da4018 test_actor: add unittests for SimActor 
* also implicitly tests for the access of signals during simulation that are
not referenced in any statements

* before, if the busy signal is never used, it is stripped
  and could not be accessed in simulation
 2015-03-21 10:02:10 +01:00
Robert Jordens
5f045b7649 sim: keep track of unreferenced items 
* items that are never referenced in any statements do not end up in the
namespace or in the verilog

* this memorizes items if they can not be found in the namespace and keeps
track of their values
 2015-03-21 10:02:10 +01:00
Florent Kermarrec
9107710f03 litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
Robert Jordens
ec465959d0 pipistrello: add user reset 
apparently needed for flashed bitstream, xiped bios, mor1kx
 2015-03-19 19:01:06 +01:00
Robert Jordens
a10875a3b7 pipistrello: fix flash, ddram pin naming 2015-03-19 19:01:06 +01:00
Robert Jordens
4fe888702d pipistrello: switch is a button 2015-03-19 18:56:49 +01:00
Robert Jordens
47ea451315 pipistrello: compress and load bitstream at 6MHz 2015-03-19 18:48:45 +01:00
Robert Jordens
860b72c8b6 pipistrello: rename sdram->ddram 2015-03-19 18:48:22 +01:00
Florent Kermarrec
82fe83a1c4 sdram: raise NotImplementedError if Minicon is used others memories than SDR (not functional for now) 2015-03-19 16:08:03 +01:00
Florent Kermarrec
9f2e5cd7b6 targets/kc705: add external reset 2015-03-19 15:58:04 +01:00
Florent Kermarrec
84b631c929 liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc 2015-03-19 14:52:02 +01:00
Florent Kermarrec
6bdf60567c liteeth/mac/core: fix hw_preamble_crc register generation 2015-03-19 13:03:27 +01:00
Sebastien Bourdeauducq
7fa1cd72a8 fhdl/verilog: fix dummy signal initial event 2015-03-19 00:24:30 +01:00
Florent Kermarrec
3aee58f484 mibuild/lattice/diamond: add verilog include path (thanks Lattice's FAE since it's not documented) 2015-03-18 18:54:22 +01:00
Florent Kermarrec
236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00
Florent Kermarrec
5a9afee234 fhdl/specials/memory: use $readmemh to initialize memories 2015-03-18 15:27:01 +01:00
Florent Kermarrec
c0fb0ef600 fhdl/verilog: change the way we initialize reg: reg name = init_value; 
This allows simplifications (init in _printsync and _printinit no longer needed)
 2015-03-18 15:05:26 +01:00
Florent Kermarrec
ea9c1b8e69 fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code" 
This probably breaks simulation with Icarus Verilog (and others simulators?)
 2015-03-18 14:59:22 +01:00
Florent Kermarrec
2fc2f8a6c0 migen/genlib/io: use 0 instead of Signal() for default rst value (immutable thanks sb) 2015-03-18 14:41:43 +01:00
Sebastien Bourdeauducq
bdc47b205a Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it)" 
This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e453.
 2015-03-18 12:08:25 +01:00
Florent Kermarrec
cb4be52922 targets: add Lattice ECP3 versa 2015-03-17 19:09:43 +01:00
Florent Kermarrec
89fefef3f8 genlib/io: add optional external rst to CRG 2015-03-17 16:22:22 +01:00
Florent Kermarrec
70f1f96fda litescope/drivers: do not build regs when addrmap is None 2015-03-17 16:04:31 +01:00
Florent Kermarrec
a266deb58e LiteXXX cores: fix frequency print in test/test_regs.py 2015-03-17 16:01:25 +01:00
Florent Kermarrec
d2cb41bc63 LiteXXX cores: convert port parameter to int if is digit in test/make.py 2015-03-17 15:58:21 +01:00
Florent Kermarrec
500e58ce7d mibuild/platform/versa: fix clock_constraints 2015-03-17 15:25:10 +01:00
Florent Kermarrec
e07b7f632c mibuild/lattice: use ODDRXD1 and new synthesis directive 2015-03-17 14:59:36 +01:00
Florent Kermarrec
b7d7fe1a4c fhdl/special: add optional synthesis directive (needed by Synplify Pro) 2015-03-17 14:59:05 +01:00
Florent Kermarrec
022ac26c22 mibuild/lattice: add LatticeAsyncResetSynchronizer 2015-03-17 12:42:36 +01:00
Florent Kermarrec
2327710387 liteeth/phy/gmii : set tx_er to 0 only if it exits 2015-03-17 12:24:06 +01:00
Florent Kermarrec
408d0fd2dd liteeth: use default programmer in make.py 2015-03-17 12:12:21 +01:00
Florent Kermarrec
ec6ae75065 liteeth: use CRG from Migen in base example 2015-03-17 12:11:51 +01:00
Florent Kermarrec
c06ab82f13 mibuild/platforms/versa: add ethernet clock constraints 2015-03-17 12:04:00 +01:00
Florent Kermarrec
a874f85854 litescope: use CRG from Migen 2015-03-17 11:52:54 +01:00
Florent Kermarrec
ba2aeb08be mibuild/platforms/versa: add rst_n 2015-03-17 11:51:34 +01:00
Florent Kermarrec
6dd8d89c6c mibuild/lattice: fix LatticeDDROutput 2015-03-17 09:40:25 +01:00
Florent Kermarrec
b2f32ad124 targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains) 2015-03-17 01:07:44 +01:00
Florent Kermarrec
9adf3f02f2 fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable code 
it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
 2015-03-17 00:40:26 +01:00
Florent Kermarrec
e946f6e453 fhdl/verilog: do not use initial begin in _printinit (not accepted by all synthesis tools ex: Synplify Pro does not accept it) 2015-03-16 23:47:07 +01:00
Florent Kermarrec
faf185d58d liteeth: make gmii phy generic 2015-03-16 23:04:37 +01:00