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litex
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100 Commits 40 Branches 14 Tags 51 MiB
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100 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 8ad251c94c Connect Ethernet IRQ 2012-05-20 23:48:41 +02:00
Sebastien Bourdeauducq 4e18e45686 Add Ethernet MAC 2012-05-20 00:30:03 +02:00
Sebastien Bourdeauducq 7d18736ff2 Update gitignore 2012-05-17 01:42:08 +02:00
Sebastien Bourdeauducq 79124d822b Identifier 2012-05-17 01:41:41 +02:00
Sebastien Bourdeauducq 141269b384 Get CSR base addresses from include file 2012-05-16 10:36:46 +02:00
Sebastien Bourdeauducq bb798176fc Common include files 2012-05-16 10:20:04 +02:00
Sebastien Bourdeauducq b6aa40d845 bios: automatically enable hardware memory controller and test memory 2012-05-15 19:29:26 +02:00
Sebastien Bourdeauducq 425c8b8e70 asmicon/multiplexer: fix read tag delay 2012-05-15 13:13:40 +02:00
Sebastien Bourdeauducq 7ecfd60368 bios: more DDR diagnostic functions 2012-05-14 20:07:57 +02:00
Sebastien Bourdeauducq 2ccdade88e tb/asmicon_wb: better access pattern 2012-04-30 19:08:31 -05:00
Sebastien Bourdeauducq 87ee4baaf0 tb/asmicon_wb: test asmicon with wishbone bridge 2012-04-26 17:53:05 -05:00
Sebastien Bourdeauducq 902908bd3b tb/asmicon: do not keep files 2012-04-26 17:21:10 -05:00
Sebastien Bourdeauducq 19b1cc2529 Remove uses of pads, new constraints system 2012-04-02 19:22:17 +02:00
Sebastien Bourdeauducq d2c4afe66c asmicon: various fixes. Now produces convincing refresh/read sequences. 2012-04-01 23:24:24 +02:00
Sebastien Bourdeauducq f5671c566f tb/asmicon: global test bench 2012-04-01 23:23:45 +02:00
Sebastien Bourdeauducq 185bd66ee4 tb/asmicon: bankmachine test bench 2012-03-31 18:11:29 +02:00
Sebastien Bourdeauducq b1e5b9ef36 tb/asmicon/bankmachine: test buffer and NACK 2012-03-31 10:06:44 +02:00
Sebastien Bourdeauducq c129c98e10 tb/asmicon/bankmachine: selector test bench 2012-03-31 09:56:22 +02:00
Sebastien Bourdeauducq ac7d89a4fe asmicon/bankmachine: fixes 2012-03-31 09:55:52 +02:00
Sebastien Bourdeauducq bccc5f5c21 tb: remove obsolete norflash test bench 2012-03-30 16:41:12 +02:00
Sebastien Bourdeauducq c6a4a8f462 tb/asmicon: refresher test 2012-03-30 16:40:51 +02:00
Sebastien Bourdeauducq cd82f16806 asmicon/refresher: fix refresh sequence done signal 2012-03-30 16:26:50 +02:00
Sebastien Bourdeauducq ab799b874f tools: new flterm 2012-03-21 09:11:43 +01:00
Sebastien Bourdeauducq c26efa28ca asmicon: multiplexer (untested) 2012-03-18 22:11:01 +01:00
Sebastien Bourdeauducq 0e00837f42 asmicon: move slot time to timing settings 2012-03-18 14:57:31 +01:00
Sebastien Bourdeauducq b1eb919ad2 asmicon: bank machine (untested) 2012-03-18 00:12:03 +01:00
Sebastien Bourdeauducq 7c377880fa asmicon: refresher (untested) 2012-03-15 20:29:26 +01:00
Sebastien Bourdeauducq e3ef121440 norflash: use new timeline API 2012-03-15 20:26:04 +01:00
Sebastien Bourdeauducq 7b14e0bd05 asmicon: skeleton 2012-03-14 18:26:05 +01:00
Sebastien Bourdeauducq 8d4a42887e ddrphy: working on hardware, simulation a bit messed up 2012-02-24 15:44:51 +01:00
Sebastien Bourdeauducq baba267db6 ddrphy: request wrdata_en/rddata_en at the same time as the command 2012-02-24 15:14:58 +01:00
Sebastien Bourdeauducq 17b2588321 ddrphy: reads OK, write data coming out 1/2 cycle too late 2012-02-24 15:05:52 +01:00
Sebastien Bourdeauducq a363eb4a36 ddrphy: partly working 2012-02-24 13:54:10 +01:00
Sebastien Bourdeauducq 3179a27d14 dfii: set data mask 2012-02-23 22:00:51 +01:00
Sebastien Bourdeauducq 92ac69bae3 dfii: new design 2012-02-23 21:21:07 +01:00
Sebastien Bourdeauducq b3ca952a39 s6ddrphy: read path OK in simulation 2012-02-21 17:38:40 +01:00
Sebastien Bourdeauducq b4e041ecf1 s6ddrphy: write path OK in simulation 2012-02-20 23:55:20 +01:00
Sebastien Bourdeauducq ce51653381 s6ddrphy: generate DQ/DQS/DM OE 2012-02-20 16:13:56 +01:00
Sebastien Bourdeauducq cbc3b7fa83 s6ddrphy: DQ/DQS/DM SERDES 2012-02-20 13:45:57 +01:00
Sebastien Bourdeauducq 4c1e18a9b5 s6ddrphy: clock, address and command 2012-02-19 20:49:56 +01:00
Sebastien Bourdeauducq f35cd4a85b Prepare for new DDR PHY 2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq 1e4e092a55 bios: fix function prototypes 2012-02-18 21:06:35 +01:00
Sebastien Bourdeauducq 026457a98c Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately. 2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq 5bc840b9c1 DFI injector (untested) 2012-02-17 23:50:10 +01:00
Sebastien Bourdeauducq c38de34a21 bios: DDR initialization skeleton 2012-02-17 18:47:04 +01:00
Sebastien Bourdeauducq e5927e265f bios: add flash target using m1nor 2012-02-17 18:16:29 +01:00
Sebastien Bourdeauducq 48ddbf0c85 Add build Makefile and JTAG load script 2012-02-17 18:09:48 +01:00
Sebastien Bourdeauducq c387ce7ce5 Map DDR PHY controls in CSR 2012-02-17 17:34:59 +01:00
Sebastien Bourdeauducq 5d1dad583b Connect DDR PHY 
Doesn't do much for the moment, just to check synthesis/P&R.
 2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq cdd58e023b s6ddrphy: use single-ended DQS 2012-02-17 10:53:58 +01:00