Florent Kermarrec
|
dbaeaf7833
|
remove trailing whitespaces
|
2014-10-17 17:08:46 +08:00 |
Sebastien Bourdeauducq
|
f658802ff8
|
replace use of __dict__ with dir()/xdir()
|
2013-11-02 16:03:47 +01:00 |
Sebastien Bourdeauducq
|
0e195da3c0
|
bank/csrgen: add get_offset function to pre-calculate register addresses
|
2013-08-02 23:05:54 +02:00 |
Sebastien Bourdeauducq
|
246b860a85
|
csr: new data width API
|
2013-07-28 16:33:36 +02:00 |
Sebastien Bourdeauducq
|
70ffe86356
|
New migen.fhdl.std to simplify imports + len->flen
|
2013-05-22 17:11:09 +02:00 |
Sebastien Bourdeauducq
|
c4f4143591
|
New CSR API
|
2013-03-30 17:28:41 +01:00 |
Sebastien Bourdeauducq
|
c4c4765a4e
|
bank/csrgen/BankArray: retain name information
|
2013-03-25 14:44:15 +01:00 |
Sebastien Bourdeauducq
|
fc883198ae
|
bank/csrgen/BankArray: create banks in sorted order
|
2013-03-13 23:07:44 +01:00 |
Sebastien Bourdeauducq
|
68fe4c269c
|
bank/csrgen: BankArray
|
2013-03-10 00:45:16 +01:00 |
Sebastien Bourdeauducq
|
62187aa23d
|
migen/bank: do not create interface in default param
|
2012-12-06 17:28:28 +01:00 |
Sebastien Bourdeauducq
|
e89c66bf14
|
bank/csrgen: interface -> bus
|
2012-12-06 17:15:34 +01:00 |
Sebastien Bourdeauducq
|
6eebfce44a
|
Refactor Case
|
2012-11-29 01:11:15 +01:00 |
Sebastien Bourdeauducq
|
fee22a4631
|
Remove Constant
|
2012-11-28 23:18:43 +01:00 |
Sebastien Bourdeauducq
|
85081793cf
|
bank: remove RE signal for field registers
|
2012-10-09 19:07:53 +02:00 |
Sebastien Bourdeauducq
|
e410973352
|
bank: support for atomic writes
|
2012-10-08 18:43:18 +02:00 |
Sebastien Bourdeauducq
|
4164fb4ac9
|
bus/csr: configurable data width
|
2012-08-26 21:19:34 +02:00 |
Sebastien Bourdeauducq
|
b9c533be51
|
bank/csrgen: allow specifying existing CSR interface
|
2012-04-06 14:59:09 +02:00 |
Sebastien Bourdeauducq
|
d8d4e81b6e
|
bank/csrgen: fix RE generation
|
2012-02-18 18:56:18 +01:00 |
Sebastien Bourdeauducq
|
55a265d967
|
bank: add RE signal for registers made of fields
|
2012-02-17 23:52:06 +01:00 |
Sebastien Bourdeauducq
|
ef7aea0f31
|
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
|
2012-02-15 18:23:31 +01:00 |
Sebastien Bourdeauducq
|
91e279ee04
|
bank/csrgen: use new bus API
|
2012-02-15 16:42:17 +01:00 |
Sebastien Bourdeauducq
|
8a61d9d121
|
bus/csr: Rename a->adr d->dat to be consistent with the other buses
|
2012-02-13 21:46:39 +01:00 |
Sebastien Bourdeauducq
|
3a2a0c4dd8
|
bank: support registers larger than the bus word width
|
2012-02-06 16:15:27 +01:00 |
Sebastien Bourdeauducq
|
f3ddfffc47
|
bank: refactoring
|
2012-02-06 13:55:50 +01:00 |
Sebastien Bourdeauducq
|
1a86f26a66
|
bank/csrgen: use enumerate
|
2012-02-06 11:18:30 +01:00 |
Sebastien Bourdeauducq
|
107f03fd4b
|
Remove uses of declare_signal
|
2011-12-18 21:47:48 +01:00 |
Sebastien Bourdeauducq
|
135a2eb868
|
bank: support raw registers
|
2011-12-18 00:28:04 +01:00 |
Sebastien Bourdeauducq
|
1a845d4553
|
32-device, 8-bit CSR bus
|
2011-12-17 15:54:49 +01:00 |
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
Sebastien Bourdeauducq
|
7582b76406
|
bank: fix csrgen address decoder
|
2011-12-11 20:15:30 +01:00 |
Sebastien Bourdeauducq
|
ec51f09c98
|
Case support + register bank generator
|
2011-12-05 17:43:56 +01:00 |