120 commits

Author	SHA1	Message	Date
Florent Kermarrec	8e04ef7b95	test minicon with de0nano (OK) and fix missing self in gensoc	2015-02-27 20:00:16 +01:00
Florent Kermarrec	f1200d6388	gensoc: move I/O for rom initialization to make.py	2015-02-27 19:48:07 +01:00
Florent Kermarrec	e07e124118	sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir ... We will maybe move things, but at least it's in MiSoC now	2015-02-27 17:07:44 +01:00
Florent Kermarrec	07b9cabd0d	gensoc: make it more generic (a SoC does not necessarily have a CPU)	2015-02-27 16:39:00 +01:00
Florent Kermarrec	be0eb8d265	use cachesize reported in wishbone2lasmi	2015-02-27 14:13:38 +01:00
Florent Kermarrec	9814001c79	create cpu dir and move lm32/mor1kx in it	2015-02-27 10:51:03 +01:00
Florent Kermarrec	9f636f7985	move memtest to sdram	2015-02-27 10:47:54 +01:00
Florent Kermarrec	b817cf49b3	replace self._r_register by self._register in all CSR declaration	2015-02-27 10:36:09 +01:00
Florent Kermarrec	77a6f580e2	gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts	2015-02-27 10:23:02 +01:00
Florent Kermarrec	617bc70d7f	liteeth: move doc	2015-02-27 09:15:54 +01:00
Robert Jordens	c9ed38dec8	gensoc: missing self.	2015-02-26 21:32:11 -07:00
Florent Kermarrec	09fbbca53e	gensoc: cpus now directly add their verilog sources	2015-02-26 20:49:21 +01:00
Florent Kermarrec	5e8a0c496d	gensoc: add mem_map and mem_decoder to avoid duplications	2015-02-26 20:12:27 +01:00
Florent Kermarrec	5ac5ffe359	gensoc: get platform_id from platform	2015-02-26 19:07:19 +01:00
Florent Kermarrec	02b3f51382	liteeth: fix example_designs generation	2015-02-26 10:23:38 +01:00
Florent Kermarrec	00862a383c	liteeth: fix import (from liteeth --> from misoclib.liteeth)	2015-02-26 09:48:37 +01:00
Florent Kermarrec	60effe1d95	move files to liteeeth and create example_designs directory	2015-02-26 09:35:14 +01:00
Sebastien Bourdeauducq	658cb0e405	merge liteeth	2015-02-25 10:35:39 -07:00
Sebastien Bourdeauducq	8015d12692	move files for misoc integration	2015-02-25 10:34:11 -07:00
Florent Kermarrec	0a38b8c74a	add LiteX external core and remove ethmac	2015-02-18 10:43:44 -07:00
Florent Kermarrec	9ebb8f8022	remove verilog and move mxcrg.v to misoclib/mxcrg	2015-02-18 10:40:30 -07:00
Florent Kermarrec	5500c41915	move lm32/mor1kx submodules to extcores	2015-02-18 10:39:18 -07:00
Florent Kermarrec	4c9554b65c	gensoc: call do_exit after SoC is built	2015-02-18 10:38:14 -07:00
Florent Kermarrec	da13bd536e	gensoc: add csr_data_width and csr_address_width as parameters In some case we want to have mode than 32 CSR or and csr_data_width != 8	2015-02-14 03:24:23 -08:00
Florent Kermarrec	9bb7e6d0ab	ethmac: improve testbenchs	2014-12-21 17:37:25 +08:00
Sebastien Bourdeauducq	aac34f011f	gensoc: support user-defined CSR regions	2014-11-30 22:29:26 +08:00
Sebastien Bourdeauducq	8ae3a00a94	gensoc: simplify WB address decoding	2014-11-30 22:05:51 +08:00
Sebastien Bourdeauducq	4189440eef	minicon: small simplifications	2014-11-28 08:28:39 +08:00
Yann Sionneau	edb1622668	spiflash: BB write support	2014-11-27 23:10:39 +08:00
Sebastien Bourdeauducq	bab6bb7c4a	gensoc: fix align	2014-11-27 23:05:36 +08:00
Sebastien Bourdeauducq	2cd80990e4	minicon: fix use of phy phases	2014-11-27 22:13:17 +08:00
Sebastien Bourdeauducq	8418ccafdc	minicon: remove unused signals and fix indent	2014-11-27 22:12:05 +08:00
Yann Sionneau	cf92821fcf	Refactor directory hierarchy of sdram phys and controllers	2014-11-27 22:09:10 +08:00
Yann Sionneau	f33b285af1	Minicon: small SDRAM controller	2014-11-27 22:09:03 +08:00
Florent Kermarrec	5202f89db1	ethmac/last_be: remove fake signal (fixed in Migen)	2014-11-21 14:48:17 -08:00
Sebastien Bourdeauducq	b7028848b2	ethmac: use new EndpointDescription API	2014-11-20 22:32:32 -08:00
Sebastien Bourdeauducq	33530e0921	ethmac: style/renaming	2014-11-20 18:01:48 -08:00
Florent Kermarec	603c2641bb	new Ethernet MAC	2014-11-20 16:47:22 -08:00
Florent Kermarrec	8e4b89849c	use new direct access on endpoints	2014-10-20 23:13:37 +08:00
Florent Kermarrec	34ed315a48	remove trailing whitespaces	2014-10-17 17:14:40 +08:00
Sebastien Bourdeauducq	e53fb88b85	uart: minor cleanup and fix	2014-10-10 15:33:27 +08:00
Florent Kermarrec	5e5f436aa6	uart: split it and use dataflow ... This make the code easier to understand and allow the reuse of UARTRX & UARTTX on designs without CPU (e.g miscope).	2014-10-10 15:24:47 +08:00
Florent Kermarrec	c0c17030fd	spi_flash: simplify usage by removing cmd, cmd_width, addr_width parameters	2014-09-04 15:23:39 +08:00
Sebastien Bourdeauducq	36434b62f0	sdram: merge DFII_PIX_RDDATA_SIZE and DFII_PIX_WRDATA_SIZE	2014-09-03 15:02:38 +08:00
Sebastien Bourdeauducq	a7b4550e59	sdramphy/initsequence: cleanup and expose DDR3 MR1 value	2014-09-03 14:21:30 +08:00
Florent Kermarrec	114890ee80	sdramphy/initsequence: clean up mr1/mr2 computation on DDR3 and enable Dynamic ODT	2014-09-02 10:54:29 +08:00
Sebastien Bourdeauducq	2234f50223	k7ddrphy: add bitslip control for incoming DQ	2014-09-01 19:54:39 +08:00
Sebastien Bourdeauducq	5483b37c8f	k7ddrphy: write leveling and read calibration support	2014-08-31 21:54:28 +08:00
Sebastien Bourdeauducq	19abe2b888	k7ddrphy: do not register T at SERDES (fixes timing problem)	2014-08-31 21:53:35 +08:00
Sebastien Bourdeauducq	541e5abbc7	k7ddrphy: update comment	2014-08-22 19:02:57 +08:00