8e07e1a099
build/microsemi/libero_soc: associate .pdc to place and route tool.
...
For constraint to be applied, we also to associate them with the tool that will use it.
2018-11-19 08:07:36 +01:00
5137c2bf88
test/test_targets: update
2018-11-17 17:36:57 +01:00
a5ed42ec68
soc/interconnect/stream: add Gearbox
2018-11-17 17:29:45 +01:00
11d536dc4d
test: remove test_bitslip (integrated in migen)
2018-11-17 17:29:09 +01:00
a25645afa6
utils: add litex_read_verilog utility
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generate Migen's modules from verilog files
2018-11-16 16:09:44 +01:00
a538d36268
create utils directory and move the litex utils to it
2018-11-16 14:37:19 +01:00
45ec78e93a
build/microsemi/libero_soc: able to generate design script (tcl) and design constraint (pdc) for libero soc / avalanche board.
2018-11-16 12:19:03 +01:00
4cb6583b4e
build: add microsemi template for polarfire fpgas support
2018-11-15 18:21:41 +01:00
bc173380f2
Merge pull request #126 from mithro/toolchain-fix
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lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.
2018-11-13 16:20:57 -08:00
b1425ba85f
lattice/icestorm: Add toolchain_path so it doesn't end up kwargs.
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Fixes the following error;
```
make[1]: Leaving directory `/home/travis/build/mithro/litex-buildenv/build/ice40_hx8k_b_evn_base_lm32.lite/software/stub'
Traceback (most recent call last):
File "./make.py", line 164, in <module>
main()
File "./make.py", line 148, in main
vns = builder.build(**dict(args.build_option))
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/builder.py", line 171, in build
toolchain_path=toolchain_path, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/soc/integration/soc_core.py", line 389, in build
return self.platform.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 29, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/icestorm.py", line 139, in build
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/lattice/platform.py", line 26, in get_verilog
**kwargs)
File "/home/travis/build/mithro/litex-buildenv/third_party/litex/litex/build/generic_platform.py", line 368, in get_verilog
create_clock_domains=False, **kwargs)
TypeError: convert() got an unexpected keyword argument 'toolchain_path'
```
2018-11-13 16:18:08 -08:00
af25bf2bc0
soc_core: check for cpu before checking interrupt
2018-11-13 16:17:49 +01:00
b4bdf2a023
cores/clock/S7: just reset the generated clock, not the PLL/MMCM
2018-11-13 14:47:04 +01:00
86fd945bc3
bios/main: fix typo on mor1kx
2018-11-13 11:16:06 +01:00
af95028574
cpu/mor1kx: use clang only for linux variant
2018-11-13 11:09:39 +01:00
04523bc28a
xilinx/vivado: fix migen merge
2018-11-12 16:31:51 +01:00
f3343c46fc
platforms: remove versaecp55g_sdram
2018-11-12 12:45:33 +01:00
58414b1819
build/xilinx/vivado: merge migen change
2018-11-12 12:00:30 +01:00
a7f17f9915
build: use default toolchain_path on all backend when passed value is None
2018-11-12 11:48:30 +01:00
eed1d5cb2e
generic_platform: use set for sources
2018-11-12 11:47:39 +01:00
665fff8390
build: merge more migen changes
2018-11-12 11:26:35 +01:00
70f48775de
platforms/versa_ecp5: import migen changes
2018-11-12 10:52:28 +01:00
4ff241b981
targets/ulx3s,versa_ecp5: prjtrellis toolchain renamed to trellis
2018-11-12 10:47:33 +01:00
cb86728ad1
build/lattice: import changes from migen
2018-11-12 10:46:49 +01:00
8574c62f75
targets/versa_ecp5: increase sys_clk_freq to 50MHz
2018-11-12 10:12:10 +01:00
a752dafb14
targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
2018-11-12 09:45:59 +01:00
87c7d23d16
targets/ulx3s: for now revert to 25MHz clock/no pll
2018-11-12 09:44:32 +01:00
d1baae36a6
platforms/versa_ecp5: add ecp5 soc hat ios
2018-11-12 09:43:31 +01:00
b3bf1c9517
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-11-12 08:12:07 +01:00
1be6762dfe
Merge pull request #125 from daveshah1/trellis_sdram
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ecp5 soc hat wip
2018-11-12 08:11:57 +01:00
425ad755ec
plarforms: rename versa/versaecp55g to versa_ecp3/versa_ecp5
2018-11-12 08:06:22 +01:00
c57aa545ca
targets/ulx3s: get memtest working by disabling sdram refresh
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Will need to be fixed...
2018-11-09 18:40:14 +01:00
9a6447172a
soc/integration/soc_sdram: allow using axi interface with litedram
2018-11-09 15:42:34 +01:00
416bdb6483
boards/platforms: add avalanche polarfire board ios definition
2018-11-08 18:24:12 +01:00
f08f80bed1
working on Versa-5G dram
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-06 14:39:25 +00:00
fc0d5c3963
bios/sdram: iterate multiple time for write leveling and add vote to eliminate transcients
2018-11-05 18:44:28 +01:00
09f962fdc4
target/kcu105: add reset button
2018-11-05 18:41:49 +01:00
169f8d8cb5
boards/platforms/kcu105: fix sdram/dq pin swap
2018-11-05 17:01:42 +01:00
d78d5d3e7f
Debugging ULX3S SDRAM
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Signed-off-by: David Shah <dave@ds0.me>
2018-11-05 11:54:22 +00:00
2624ba48c2
bios/sdram: replace DDR3_MR1 constant with DDRX_MR1
2018-11-05 10:47:25 +01:00
6be74aa17f
boards/targets: add kcu105
2018-11-05 10:44:50 +01:00
93c623251b
Merge pull request #122 from daveshah1/trellis_ulx3s
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Switch Trellis build to use LPF constraints; working on ULX3S
2018-11-02 19:59:23 +01:00
00ef8240ef
Merge pull request #124 from jfng/master
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build/sim/verilator: don't use --threads when $(THREADS) is unset
2018-11-02 17:46:04 +01:00
dcbe759b64
build/sim/verilator: don't use --threads when $(THREADS) is unset
2018-11-02 14:22:44 +01:00
6f38213acc
boards/platforms/kc705: add user_sma_mgt_refclk
2018-11-01 10:52:01 +01:00
4cdd679908
Merge pull request #123 from cr1901/prv32-min
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PicoRV32 Enhancements
2018-11-01 10:45:32 +01:00
e56f71824d
libbase/crt0-picorv32: Emulate support for a relocatable IRQ vector (hardcoded at synthesis time).
2018-11-01 05:02:04 -04:00
f32121e0e1
cpu/picorv32: IRQ vector needs to be moved to 16 bytes after the RESET vector.
2018-11-01 02:23:01 -04:00
77389d27b5
libbase/crt0-picorv32: Ensure BSS is cleared on boot.
2018-11-01 02:18:03 -04:00
f7969b660a
cores/clock: add with_reset parameter (default to True)
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In some cases we want to generate the reset externally.
2018-10-31 16:23:23 +01:00
0729b3a059
ulx3s: Connect SDRAM clock
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Signed-off-by: David Shah <dave@ds0.me>
2018-10-31 13:29:35 +00:00
Florent Kermarrec
Tim Ansell
David Shah
Jean-François Nguyen
William D. Jones