Florent Kermarrec
|
041483dbe1
|
soc/integration/builder: only copy Makefiles when not using symlinks
|
2015-11-14 03:36:46 +01:00 |
|
Florent Kermarrec
|
a2aa5726bf
|
soc/cores: remove liteeth_mini and use liteeth
|
2015-11-14 03:22:43 +01:00 |
|
Florent Kermarrec
|
16ba646b1b
|
add TODOs
|
2015-11-14 03:15:10 +01:00 |
|
Florent Kermarrec
|
cf4c7da2e7
|
fix soc/integration/soc_core.py
|
2015-11-14 02:44:12 +01:00 |
|
Florent Kermarrec
|
032f5a9620
|
soc/interconnect: add stream_sim
|
2015-11-14 00:43:49 +01:00 |
|
Florent Kermarrec
|
ba959c832d
|
soc/interconnect: rename packet to stream_packet
|
2015-11-14 00:42:58 +01:00 |
|
Florent Kermarrec
|
1158b98fdd
|
doc: update logo
|
2015-11-13 23:40:27 +01:00 |
|
Florent Kermarrec
|
fc3ffe87ac
|
for now use our fork of migen (to be able to simulate our designs)
|
2015-11-13 18:31:46 +01:00 |
|
Florent Kermarrec
|
ae3d54499a
|
litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented
|
2015-11-13 14:44:16 +01:00 |
|
Florent Kermarrec
|
7d6cee6751
|
soc/interconnect/stream: add BufferizeEndpoints
|
2015-11-12 18:54:15 +01:00 |
|
Florent Kermarrec
|
83427c87cd
|
soc/interconnect/stream: add Pipeline
|
2015-11-12 01:41:23 +01:00 |
|
Florent Kermarrec
|
81c6facca2
|
soc/interconnect/stream: reintroduce params
|
2015-11-12 01:12:15 +01:00 |
|
Florent Kermarrec
|
f6b30fcae2
|
soc/interconnect: add packet
|
2015-11-12 00:54:40 +01:00 |
|
Florent Kermarrec
|
525da89c7d
|
soc/interconnect: add wishbonebridge and uart bridge
|
2015-11-12 00:52:36 +01:00 |
|
Florent Kermarrec
|
89b189ce4a
|
soc/interconnect/stream: reintroduce PipelinedActor/Buffer
|
2015-11-12 00:51:32 +01:00 |
|
Florent Kermarrec
|
194e6137ae
|
soc/integration/soc_core: add support for SoCs without CPU
|
2015-11-12 00:50:23 +01:00 |
|
Florent Kermarrec
|
57c0f85656
|
README: update
|
2015-11-11 17:38:12 +01:00 |
|
Florent Kermarrec
|
c076c2cbd6
|
boards/targets: remove papilio_pro/pipistrello
|
2015-11-11 17:38:03 +01:00 |
|
Florent Kermarrec
|
352cb91688
|
soc/integration/builder: add use_symlinks parameter and desactivate symlinks by default
On windows machines, console need to be run as Administrator to create symlinks which is bit painful.
|
2015-11-11 17:37:28 +01:00 |
|
Florent Kermarrec
|
1cec0f8086
|
boards/targets/sim: add ethernet support
|
2015-11-11 14:23:39 +01:00 |
|
Florent Kermarrec
|
1f6983da2c
|
soc/cores/liteeth_mini: add phy model for verilator simulation
|
2015-11-11 14:22:27 +01:00 |
|
Florent Kermarrec
|
481163b233
|
soc/cores: reintroduce liteeth_mini (until we switch to liteeth)
|
2015-11-11 14:01:48 +01:00 |
|
Florent Kermarrec
|
d0ec57add6
|
doc: add logo
|
2015-11-11 13:36:29 +01:00 |
|
Florent Kermarrec
|
714a3d88e2
|
add LICENSE, update copyrights, add Migen install instructions
|
2015-11-11 13:22:39 +01:00 |
|
Florent Kermarrec
|
bda196fbc8
|
soc/software/bios/sdram: split memtest and allow external #define of memtest sizes
|
2015-11-11 13:10:03 +01:00 |
|
Florent Kermarrec
|
619cd8e695
|
avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules
|
2015-11-11 12:10:55 +01:00 |
|
Florent Kermarrec
|
3f43a49382
|
soc: merge with misoc 3fcc4f116c3292020cb811d179e45ae45990101b
changes:
-software/bios: remove dataflow
-cores/identifier: replace with user-defined string
-interconnect/CSRBankArray: support read-only mappings
-targets: Added Numato Mimas V2 target
-Our libunwind changes were merged upstream.
-wishbone: update TODO
-replace Counter in Converters
-Fix CSRBankArray
-flterm: properly exit on ^C.
|
2015-11-10 16:51:51 +01:00 |
|
Florent Kermarrec
|
3297210e48
|
boards/targets/sim: get SDRAM working in simulation with sdram/model
|
2015-11-10 12:57:23 +01:00 |
|
Florent Kermarrec
|
4afe4a07e4
|
soc/software: remove memtest (should be re-written)
|
2015-11-10 12:22:08 +01:00 |
|
Florent Kermarrec
|
6764c06b62
|
soc/sofware: remove libdyld
|
2015-11-10 12:21:23 +01:00 |
|
Florent Kermarrec
|
f72e172ac3
|
soc/software: remove libunwind
|
2015-11-10 12:16:34 +01:00 |
|
Florent Kermarrec
|
85e6716b6b
|
litex/build/xilinx/programmer: remove UrJTAG and Adept
|
2015-11-10 12:01:25 +01:00 |
|
Florent Kermarrec
|
1b3cad5b09
|
README: update
|
2015-11-10 11:33:11 +01:00 |
|
Florent Kermarrec
|
a775672314
|
litex: get verilator simulation working and add sim target as example
|
2015-11-07 23:51:37 +01:00 |
|
Florent Kermarrec
|
6a0f85dc42
|
litex: reorganize things, first work working version
|
2015-11-07 17:48:55 +01:00 |
|
Florent Kermarrec
|
637634f312
|
import migen in litex/gen
|
2015-11-07 12:22:32 +01:00 |
|
Florent Kermarrec
|
8ebc9f57c6
|
Merge remote-tracking branch 'migen/master'
|
2015-11-07 12:20:50 +01:00 |
|
Florent Kermarrec
|
b028569784
|
import misoc in litex/soc
|
2015-11-07 12:19:30 +01:00 |
whitequark
|
f24e7e5b29
|
Update .gitignore.
|
2015-11-07 10:25:51 +03:00 |
Sebastien Bourdeauducq
|
6f5bf0292e
|
fhdl/verilog: create clock domains in deterministic order
|
2015-11-05 15:06:33 +08:00 |
|
Sebastien Bourdeauducq
|
306235e93d
|
libcompiler_rt: add fixunsdfdi
|
2015-11-04 17:07:10 +08:00 |
|
Sebastien Bourdeauducq
|
180ba95dd4
|
setup.py: consistent version number
|
2015-11-04 16:47:33 +08:00 |
|
Sebastien Bourdeauducq
|
1d60882f74
|
setup.py: fix version number
|
2015-11-04 16:47:02 +08:00 |
|
Sebastien Bourdeauducq
|
2de8e1de38
|
setup.py: consistent version number
|
2015-11-04 16:46:46 +08:00 |
|
Sebastien Bourdeauducq
|
1ea775efb6
|
conda: use correct branch
|
2015-11-04 16:46:28 +08:00 |
|
Sebastien Bourdeauducq
|
da171d8d0a
|
Merge 'new' branch
|
2015-11-04 16:41:34 +08:00 |
|
Sebastien Bourdeauducq
|
046b59853f
|
conda: use correct branch
|
2015-11-04 16:08:09 +08:00 |
|
Sebastien Bourdeauducq
|
ae952561aa
|
Merge 'new' branch
|
2015-11-04 16:07:20 +08:00 |
|
Sebastien Bourdeauducq
|
71fd951df2
|
integration/builder: add gateware toolchain path command line switch
|
2015-11-04 14:57:48 +08:00 |
|
Sebastien Bourdeauducq
|
56aac31304
|
build: standardize toolchain path setting
|
2015-11-04 14:55:12 +08:00 |