b157d84434
README
2012-02-14 15:43:09 +01:00
aef2e4b5e8
Use double quotes for all strings
2012-02-14 13:15:00 +01:00
5165ff7ec3
Include Wishbone to ASMI bridge
2012-02-13 23:12:57 +01:00
0654bf4583
tools: use install and /usr/local (as suggested by David Kuehling)
2012-02-08 15:09:07 +01:00
bfd2bf4ed3
tools: remove bin2hex
2012-02-08 15:08:03 +01:00
755079d7fa
libbase: blocking UART write if IRQs are enabled
2012-02-07 15:12:27 +01:00
73fce59631
software: shell from original BIOS
2012-02-07 15:02:44 +01:00
ef0667d959
software: UART RX demo
2012-02-07 14:12:33 +01:00
506ffab11a
uart: RX support
2012-02-07 14:12:23 +01:00
fb22edc06a
software: enable -Wmissing-prototypes
2012-02-07 13:02:06 +01:00
63f6dece56
software: use the Clang/LLVM compiler
2012-02-07 12:52:34 +01:00
a40b0ea175
software: fix size_t and ptrdiff_t
2012-02-07 12:06:49 +01:00
494c383fa8
software: remove unnecessary IRQ acks
2012-02-07 00:07:25 +01:00
b6b1901bb8
LM32: make IP read-only and interrupt lines level-sensitive
2012-02-07 00:07:12 +01:00
4aaf48afb0
software: interrupt driven UART working
2012-02-06 23:53:29 +01:00
58f4f78d2c
sram: fix sub-word write
2012-02-06 23:13:35 +01:00
5cde57cb65
software: use new UART
2012-02-06 17:53:41 +01:00
33f1c456bf
top: connect UART IRQ
2012-02-06 17:45:40 +01:00
5dc875de69
UART: use new bank API and event manager
2012-02-06 17:45:31 +01:00
45529d5941
BIOS: hello world
2012-02-05 20:01:28 +01:00
33da32417a
Update gitignore
2012-02-05 20:01:14 +01:00
9b9a510525
Memory map
2012-02-05 19:54:08 +01:00
17cd8dd479
Add tools
2012-02-05 19:14:24 +01:00
e2317bc83b
flash: remove splash screens
2012-02-05 19:12:33 +01:00
1ad44b6571
software: dependencies the Werner way
2012-02-03 12:25:55 +01:00
1a4a6eb445
Copy some software code from the original Milkymist SoC.
...
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
2012-02-03 12:08:17 +01:00
b5cb1083ab
sram: fix WE signal
2012-02-03 10:38:17 +01:00
8a2646a549
Remove explicit bus names
2012-01-27 22:21:08 +01:00
28f00c3a9a
Add on-chip SRAM
2012-01-27 22:09:03 +01:00
6fde54c5aa
Use meaningful class names
2012-01-21 12:25:22 +01:00
f6aa95a4d0
Use new verilog.convert API
2012-01-20 23:00:11 +01:00
f8d5c27ef8
Wishbone: omit fixed LSBs
2012-01-13 17:28:58 +01:00
570ea8ccf8
convtools -> tools
2012-01-13 17:07:46 +01:00
b60abfaa4a
Convert -> convert
2012-01-05 19:27:45 +01:00
3b640c45bb
Use new syntax
2011-12-18 22:02:05 +01:00
6664af73d1
uart: new design using FHDL and bank (TX only, incomplete)
2011-12-18 00:29:37 +01:00
bb21f7584a
32-device, 8-bit CSR bus
2011-12-17 15:54:42 +01:00
1b3edd07ca
norflash tb: use get_fragment
2011-12-17 15:22:26 +01:00
0e30d67fa3
Multiply system clock
2011-12-17 15:00:18 +01:00
85fbe07b94
clkfx module
2011-12-17 15:00:11 +01:00
411e1af980
Proper reset generation
2011-12-16 22:25:26 +01:00
738b45dcbd
Support the new FHDL syntax
2011-12-16 21:30:22 +01:00
ca68097ef6
Pay a bit more attention to PEP8
2011-12-16 16:02:49 +01:00
b487e99bcf
Initial import
2011-12-13 17:33:12 +01:00
Sebastien Bourdeauducq