Florent Kermarrec
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1583cc8a40
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cpu/naxriscv: Add default value to xlen argument.
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2022-03-21 17:14:24 +01:00 |
Florent Kermarrec
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8e440dc9ea
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soc/integration: Add LiteXSocArgumentParser to be able to expose CPU parameters to user on targets.
Currently used for CPU parameters could problably be extented to simplify other parts
of the code in the future.
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2022-03-21 16:57:14 +01:00 |
Florent Kermarrec
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6ef96b17bc
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soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).
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2022-03-21 15:21:08 +01:00 |
Dolu1990
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f5d4977dde
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Merge pull request #1246 from gsomlo/gls-memtest-cast-warning
bios/memtest: fix cast warning
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2022-03-20 21:09:36 +01:00 |
Gabriel Somlo
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e5a2305269
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bios/memtest: fix cast warning
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2022-03-20 14:30:16 -04:00 |
developandplay
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884ee45c28
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Fix compilation of demo.bin on Rocket
- Adjust memory model to fix `relocation truncated` errors
- Make isr.c shared between BIOS and demo to resolve dep on `plic_init`
Based on: https://github.com/enjoy-digital/litex/issues/1168
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2022-03-20 15:39:13 +01:00 |
Dolu1990
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f565bec7f1
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cpu/naxriscv fix xlen not being hashed, improve RV64 performances
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2022-03-18 15:39:58 +01:00 |
Florent Kermarrec
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58549834ec
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tools/litex_sim: Use new get_boot_address function.
Allow litex_sim to use similar .json files than the ones used on hardware.
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2022-03-17 17:46:27 +01:00 |
Florent Kermarrec
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4036c75600
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integration/common: Add get_boot_address to get CPU boot address from json file.
Will allow litex_sim to use similar .json files than the ones used on hardware.
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2022-03-17 17:45:30 +01:00 |
Florent Kermarrec
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dd7709ed6f
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tools/litex_sim/add_sdram: origin no longer required.
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2022-03-17 16:47:02 +01:00 |
Florent Kermarrec
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05724d9fea
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cpu/naxriscv/vexriscv_smp: Declare/Add OpenSBI region in add_soc_compoents.
Avoid doing it in Linux-on-LiteX-Vexriscv.
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2022-03-17 16:28:25 +01:00 |
Florent Kermarrec
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b4db2a3ef2
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tools/litex_sim: Remove obsolete max_sdram_size parameter.
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2022-03-17 16:14:26 +01:00 |
Florent Kermarrec
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3b4a885366
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cpu/naxriscv/vexriscv_smp: Also enforce UART/Timer0 IRQs.
Avoid doing it in Linux-on-LiteX-Vexriscv and allow generating bitstreams directly from litex-boards.
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2022-03-17 16:10:34 +01:00 |
Florent Kermarrec
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e6e3a909f2
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cpu/vexriscv_smp: Set UART/Timer0 CSRs as done on NaxRiscv to ensure OpenSBI compatibility.
This also allow generating bitstreams for Linux-on-LiteX-VexRiscv directly from litex-boards.
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2022-03-17 16:00:05 +01:00 |
Florent Kermarrec
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2ec0ebe40f
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build/gowin: Add copy of bitstream to from impl to gateware directory.
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2022-03-17 09:35:34 +01:00 |
Florent Kermarrec
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148324862a
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integration/builder: Add get_bios_filename/get_bitstream_filename methods to simplify targets/projects.
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2022-03-17 09:19:41 +01:00 |
Florent Kermarrec
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e6a81ec2af
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integration/soc/add_etherbone: Set default buffer_depth to 16 (Allow LiteScope's width up to 512-bit).
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2022-03-16 16:43:28 +01:00 |
Florent Kermarrec
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371608712f
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litex_client: Add CSR Filter.
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2022-03-16 10:59:47 +01:00 |
Florent Kermarrec
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488a6d7256
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litex_client/gui: Minor changes.
- By default, always on top.
- Update register on enter.
- Add title to viewport.
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2022-03-16 09:39:04 +01:00 |
Florent Kermarrec
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1b128804ae
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tools/litex_client: Add initial and very simple GUI support.
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2022-03-15 19:19:01 +01:00 |
Dolu1990
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4896527e6f
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cpu/naxriscv fix git and add RV64 support (--xlen 64)
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2022-03-15 11:54:28 +01:00 |
enjoy-digital
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7712c8a79f
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Merge pull request #1236 from gregdavill/trellis_compress_default
build/trelis: Compress bitstream by default
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2022-03-11 21:56:41 +01:00 |
Florent Kermarrec
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43cc2ff9bb
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software/libbase/memtest: Skip memtest_addr when size < 16KB.
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2022-03-11 15:28:34 +01:00 |
Florent Kermarrec
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c851e74e09
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README: Add link to new LiteX quick tour/overview presentation.
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2022-03-10 18:13:44 +01:00 |
Florent Kermarrec
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1ebcc03a92
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soc/add_pcie: Add address_width support for 64-bit addressing.
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2022-03-10 16:09:18 +01:00 |
Greg Davill
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3de88c1aed
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build/trelis: Compress bitstream by default
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2022-03-10 13:51:14 +10:30 |
Florent Kermarrec
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f446415f68
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cpu/minerva: nMigen -> Amaranth.
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2022-03-09 11:00:50 +01:00 |
Florent Kermarrec
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9d5bf70cb2
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cpu/femtorv/firev: Remove debug displays now that validated in sim and hardware.
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2022-03-09 10:54:05 +01:00 |
Florent Kermarrec
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ece286b15d
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litex_setup: Rename --status to --freeze and generate freezed git_repos dict.
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2022-03-08 18:12:11 +01:00 |
Florent Kermarrec
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7411109f4d
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gowin/programmer: Fix copyright year.
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2022-03-08 17:25:27 +01:00 |
enjoy-digital
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72576c87fc
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Merge pull request #1234 from curliph/master
for windows/(powershell and WSL) support
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2022-03-08 17:23:05 +01:00 |
curliph
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700077e4a1
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powershell and WSL support
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2022-03-08 13:52:03 +08:00 |
curliph
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cfab857c7b
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win/powershell support.
add gowin programmer support.
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2022-03-08 13:16:01 +08:00 |
Florent Kermarrec
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7ebc7625d5
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tools/litex_client: Add --csr-csv support.
Useful to debug multi-FPGA projects.
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2022-03-07 11:42:32 +01:00 |
Florent Kermarrec
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87d5d7c87c
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cpu/firev/core: Review/Cleanup pass, also fix set_reset_address.
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2022-03-04 12:12:06 +01:00 |
enjoy-digital
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ea883909b5
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Merge pull request #1232 from sylefeb/silice-firev
Silice FireV
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2022-03-04 11:41:13 +01:00 |
Florent Kermarrec
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8ade60a55d
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soc/reset: Change the way crg_rst is set to allow possible multiple assignation in the code.
This allows user's cores to also exercise the CRG rst with code similar to:
self.comb += If(<rst_condition>, self.crg.rst.eq(1))
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2022-03-04 10:47:52 +01:00 |
sylefeb
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2d40846c34
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Merge branch 'enjoy-digital:master' into silice-firev
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2022-03-03 21:41:21 +01:00 |
enjoy-digital
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7fcecf437a
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Merge pull request #1230 from antmicro/add-cpus-to-litex_json2renode
Add CPUs to litex_json2renode script
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2022-03-03 17:33:43 +01:00 |
Florent Kermarrec
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b092d2a180
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cores/jtag: Fix chain parameter on XilinxJTAG.
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2022-03-03 16:45:20 +01:00 |
Florent Kermarrec
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e00eafd97f
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cores/ram: Add Xilinx Ultrascale+ HBM2 wrapper.
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2022-03-03 16:33:05 +01:00 |
Sylvain Lefebvre
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f5f0937493
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added firev CPU
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2022-03-03 15:07:38 +01:00 |
Michal Sieron
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c3fb321532
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tools/litex_json2renode: Add support for Minerva
|
2022-03-03 12:04:33 +01:00 |
Michal Sieron
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d86bdb71ec
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tools/litex_json2renode: Don't use generic RV32 for Ibex
|
2022-03-03 12:03:03 +01:00 |
Michal Sieron
|
35dd5554ba
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tools/litex_json2renode: Add cv32e40p support
|
2022-03-03 11:59:26 +01:00 |
enjoy-digital
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46361db135
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Merge pull request #1229 from smunaut/jtag-zynq-usp
cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
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2022-03-02 21:56:03 +01:00 |
Sylvain Munaut
|
d8df6cb27d
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cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
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2022-03-02 14:12:18 +01:00 |
Florent Kermarrec
|
4bc1691487
|
soc/cores/xadc: Update copyrights.
|
2022-03-01 14:48:02 +01:00 |
Florent Kermarrec
|
0a40616df9
|
litex_setup.py: Remove LiteHyperBus dependency (not currently used by LiteX-Boards).
We could add it back as a dependency if the simple/portable core is no longer enough for
regular use cases.
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2022-03-01 09:27:23 +01:00 |
Florent Kermarrec
|
dbde036162
|
soc/cores: Re-integrated generic/portable HyperBus/HyperRAM core from LiteHyperBus.
The generic version of the HyperRAM core is simple enough to be directly integrated in LiteX
which avoid an additional dependency.
|
2022-03-01 09:11:55 +01:00 |