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litex
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362 Commits 42 Branches 14 Tags 30 MiB
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362 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq cbc3b7fa83 s6ddrphy: DQ/DQS/DM SERDES 2012-02-20 13:45:57 +01:00
Sebastien Bourdeauducq 4c1e18a9b5 s6ddrphy: clock, address and command 2012-02-19 20:49:56 +01:00
Sebastien Bourdeauducq f35cd4a85b Prepare for new DDR PHY 2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq 1e4e092a55 bios: fix function prototypes 2012-02-18 21:06:35 +01:00
Sebastien Bourdeauducq 026457a98c Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately. 2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq 5bc840b9c1 DFI injector (untested) 2012-02-17 23:50:10 +01:00
Sebastien Bourdeauducq c38de34a21 bios: DDR initialization skeleton 2012-02-17 18:47:04 +01:00
Sebastien Bourdeauducq e5927e265f bios: add flash target using m1nor 2012-02-17 18:16:29 +01:00
Sebastien Bourdeauducq 48ddbf0c85 Add build Makefile and JTAG load script 2012-02-17 18:09:48 +01:00
Sebastien Bourdeauducq c387ce7ce5 Map DDR PHY controls in CSR 2012-02-17 17:34:59 +01:00
Sebastien Bourdeauducq 5d1dad583b Connect DDR PHY 
Doesn't do much for the moment, just to check synthesis/P&R.
 2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq cdd58e023b s6ddrphy: use single-ended DQS 2012-02-17 10:53:58 +01:00
Sebastien Bourdeauducq cc5e4ae710 clkfx: remove 2012-02-16 19:30:00 +01:00
Sebastien Bourdeauducq 204452b0d3 m1crg: make clock feedback pin bidirectional 2012-02-16 18:35:44 +01:00
Sebastien Bourdeauducq f36a45edcb lm32: compatibility with the new instance API 2012-02-16 18:35:22 +01:00
Sebastien Bourdeauducq 72f9af9d90 Generate all clocks for the DDR PHY 2012-02-16 18:02:37 +01:00
Sebastien Bourdeauducq 859c9d8849 Use new bus API 2012-02-15 16:55:13 +01:00
Sebastien Bourdeauducq 1368b666df s6ddrphy: prepare quilt 2012-02-14 15:52:39 +01:00
Sebastien Bourdeauducq b157d84434 README 2012-02-14 15:43:09 +01:00
Sebastien Bourdeauducq aef2e4b5e8 Use double quotes for all strings 2012-02-14 13:15:00 +01:00
Sebastien Bourdeauducq 5165ff7ec3 Include Wishbone to ASMI bridge 2012-02-13 23:12:57 +01:00
Sebastien Bourdeauducq 0654bf4583 tools: use install and /usr/local (as suggested by David Kuehling) 2012-02-08 15:09:07 +01:00
Sebastien Bourdeauducq bfd2bf4ed3 tools: remove bin2hex 2012-02-08 15:08:03 +01:00
Sebastien Bourdeauducq 755079d7fa libbase: blocking UART write if IRQs are enabled 2012-02-07 15:12:27 +01:00
Sebastien Bourdeauducq 73fce59631 software: shell from original BIOS 2012-02-07 15:02:44 +01:00
Sebastien Bourdeauducq ef0667d959 software: UART RX demo 2012-02-07 14:12:33 +01:00
Sebastien Bourdeauducq 506ffab11a uart: RX support 2012-02-07 14:12:23 +01:00
Sebastien Bourdeauducq fb22edc06a software: enable -Wmissing-prototypes 2012-02-07 13:02:06 +01:00
Sebastien Bourdeauducq 63f6dece56 software: use the Clang/LLVM compiler 2012-02-07 12:52:34 +01:00
Sebastien Bourdeauducq a40b0ea175 software: fix size_t and ptrdiff_t 2012-02-07 12:06:49 +01:00
Sebastien Bourdeauducq 494c383fa8 software: remove unnecessary IRQ acks 2012-02-07 00:07:25 +01:00
Sebastien Bourdeauducq b6b1901bb8 LM32: make IP read-only and interrupt lines level-sensitive 2012-02-07 00:07:12 +01:00
Sebastien Bourdeauducq 4aaf48afb0 software: interrupt driven UART working 2012-02-06 23:53:29 +01:00
Sebastien Bourdeauducq 58f4f78d2c sram: fix sub-word write 2012-02-06 23:13:35 +01:00
Sebastien Bourdeauducq 5cde57cb65 software: use new UART 2012-02-06 17:53:41 +01:00
Sebastien Bourdeauducq 33f1c456bf top: connect UART IRQ 2012-02-06 17:45:40 +01:00
Sebastien Bourdeauducq 5dc875de69 UART: use new bank API and event manager 2012-02-06 17:45:31 +01:00
Sebastien Bourdeauducq 45529d5941 BIOS: hello world 2012-02-05 20:01:28 +01:00
Sebastien Bourdeauducq 33da32417a Update gitignore 2012-02-05 20:01:14 +01:00
Sebastien Bourdeauducq 9b9a510525 Memory map 2012-02-05 19:54:08 +01:00
Sebastien Bourdeauducq 17cd8dd479 Add tools 2012-02-05 19:14:24 +01:00
Sebastien Bourdeauducq e2317bc83b flash: remove splash screens 2012-02-05 19:12:33 +01:00
Sebastien Bourdeauducq 1ad44b6571 software: dependencies the Werner way 2012-02-03 12:25:55 +01:00
Sebastien Bourdeauducq 1a4a6eb445 Copy some software code from the original Milkymist SoC. 
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
 2012-02-03 12:08:17 +01:00
Sebastien Bourdeauducq b5cb1083ab sram: fix WE signal 2012-02-03 10:38:17 +01:00
Sebastien Bourdeauducq 8a2646a549 Remove explicit bus names 2012-01-27 22:21:08 +01:00
Sebastien Bourdeauducq 28f00c3a9a Add on-chip SRAM 2012-01-27 22:09:03 +01:00
Sebastien Bourdeauducq 6fde54c5aa Use meaningful class names 2012-01-21 12:25:22 +01:00
Sebastien Bourdeauducq f6aa95a4d0 Use new verilog.convert API 2012-01-20 23:00:11 +01:00
Sebastien Bourdeauducq f8d5c27ef8 Wishbone: omit fixed LSBs 2012-01-13 17:28:58 +01:00