stone3311
54f466772b
cores/zynqmp: Fix boot helper
2023-07-05 20:14:05 +02:00
Florent Kermarrec
c58f46bb79
CHANGES: Update.
2023-07-03 18:09:56 +02:00
Florent Kermarrec
a2d44370bd
CHANGES: Update.
2023-07-03 10:56:29 +02:00
Florent Kermarrec
7fa7a4c72a
soc/add_ethernet: Review/Minor changes to TXSlots write-only mode.
2023-07-03 10:50:47 +02:00
enjoy-digital
646c917d7f
Merge pull request #1720 from sensille/tx_write_only
...
Tx write only
2023-07-03 10:45:52 +02:00
Tim 'mithro' Ansell
886994aaa4
Merge pull request #1721 from rasmuspeders1/master
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Make litex_json2renode work with default arty target SOC .json file
2023-06-30 10:05:45 -07:00
Rasmus Pedersen
26ed13a300
Assume cpu count 1 if not present
2023-06-30 13:46:08 +02:00
Rasmus Pedersen
8d33dc364f
Only add "cpu PC <opensbi_base>" if opensbi is present
2023-06-30 13:44:31 +02:00
Rasmus Pedersen
a12703b4ee
litex_json2renode: only add cpu timeProvider if time_provider exists
2023-06-29 14:13:49 +02:00
Florent Kermarrec
648c70de82
cmd_litesata: Fix help printf and update CHANGES.
2023-06-28 23:07:17 +02:00
enjoy-digital
b7cbd6c7fb
Merge pull request #1715 from gsomlo/gls-sata-multisector
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Update bios for LiteSATA multi-sector read/write changes
2023-06-28 23:03:15 +02:00
Arne Jansen
74c3ba0992
Merge branch 'enjoy-digital:master' into tx_write_only
2023-06-28 18:56:05 +02:00
Florent Kermarrec
2cdc4fb0ab
ci: Use last known working version of Verilator for Microwatt (Thanks @trabucayre).
2023-06-27 14:32:31 +02:00
Arne Jansen
5524a17702
add tx_write_only flag to add_ethernet
...
This can save some resources in case reading the tx buffer is not needed.
It also makes it easier for synthesis to infer BRAM, tested on Spartan6.
2023-06-27 09:45:50 +02:00
Nate Slager
7a7c74faa9
fix radiant bug 'Mal-formed command line - please check for extra quotes in macro' ( #1718 )
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* fix radiant bug 'Mal-formed command line - please check for extra quotes in macro'
* fix Radiant Mal-formed command line bug (more pythonic)
* (typo, rm line 159) fix Radiant Mal-formed command line bug
---------
Co-authored-by: slagernate@github.com <slagernate@github.com>
2023-06-24 08:57:44 +02:00
Gabriel Somlo
8dca488432
software/bios/cmd_litesata: add multisector read/write test
2023-06-22 17:59:18 -04:00
Gabriel Somlo
1d2eddbe37
software/bios/cmd_litesata: add multi-sector xfer between SATA and memory
...
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-06-22 17:59:18 -04:00
Gabriel Somlo
7d1e12c870
software/liblitesata: update to multi-sector read, write
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The LiteSATA gateware now supports multi-sector transfers, and expects
a sector count register to be populated by the software before a DMA
transfer is initiated.
This patch also fixes checks for `done` and `error` during writes by
using the correct `mem2sector` read function (instead of `sector2mem`,
which is for use during read operations).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-06-22 17:59:18 -04:00
Florent Kermarrec
a9d6a0c6c9
CHANGES: Update.
2023-06-22 17:40:41 +02:00
Florent Kermarrec
fbe3fcf76a
CHANGES: Update.
2023-06-21 12:46:16 +02:00
Florent Kermarrec
7b5515ced4
cores/pwm: Simplify pwm generation and avoid potential glitch on reset.
2023-06-19 23:02:50 +02:00
enjoy-digital
298ec03dae
Merge pull request #1713 from shenki/microwatt-socregion
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microwatt: Correct SoCRegion typo
2023-06-19 19:23:11 +02:00
Florent Kermarrec
d2aae18957
soc/add_pcie/MSI-X: Pass csr_ordering to LitePCIeMSIX.
2023-06-19 19:21:05 +02:00
Florent Kermarrec
94a0a5b0d8
soc/add_pcie: Add msi_width parameter to select MSI width.
2023-06-19 09:54:56 +02:00
Florent Kermarrec
a9cbb16785
soc/add_pcie: Add msi_type parameter to select MSI, MSI-Multi-Vector or MSI-X.
2023-06-19 09:45:21 +02:00
Joel Stanley
ae22f4028a
microwatt: Correct SoCRegion typo
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Fixes: 45b9636902
("integration/soc: Avoid soc_region_cls workaround and update CPUs.")
2023-06-18 21:56:31 +09:30
Florent Kermarrec
6e5651b320
CHANGES: Update.
2023-06-16 08:33:23 +02:00
Florent Kermarrec
56927ee73a
cpu/vexriscv_smp/core: Add add_synthesis_define function to add 'define SYNTHESIS to VexRiscv-SMP generated code for toolchains requiring it.
...
This was causing issue with Gowin synthesis tool and it's not yet clear how to define it from Gowin project.
So do it directly in the generated code for now until we find a better solution.
See https://github.com/enjoy-digital/litex/issues/1698 .
2023-06-15 15:45:34 +02:00
Florent Kermarrec
3d3ca05359
tools/litex_client: Fix read regression.
2023-06-14 16:59:47 +02:00
Florent Kermarrec
7a4fa58cbf
CHANGES: Update.
2023-06-13 18:37:34 +02:00
Florent Kermarrec
57840c63a3
cores/clock/xilinx_common: Add BUFH support and lower buf parameter before use to allow user to specify it in upper or lower case.
2023-06-13 13:23:47 +02:00
Florent Kermarrec
3a7aaf5124
cores/code_8b10b: Add D function.
2023-06-13 10:00:37 +02:00
Florent Kermarrec
a7ba5771b1
integration/soc/add_etherbone: Fix typo.
2023-06-09 15:18:23 +02:00
Florent Kermarrec
c6adf703a3
CHANGES.md: Update.
2023-06-06 11:09:44 +02:00
Andrew Dennison
e84881072f
software/liblitespi: fix building with debug
2023-06-06 10:02:50 +02:00
Andrew Dennison
9c426c14a2
software/liblitespi: add read_id()
2023-06-06 10:02:37 +02:00
Andrew Dennison
d0b7f54d27
build/openfpgaloader: support --fpga-part
2023-06-06 10:02:25 +02:00
Andrew Dennison
bd7b951af0
soc/software/liblitesdcard: be less verbose
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debug is now more usable:
Booting from SDCard in SD-Mode...
Booting from boot.json...
Setting SDCard clk freq to 781 KHz
CMD0: GO_IDLE
cmdevt: wait for event & 0x1
cmdevt: 00000001
00000000 00000000 00000000 00000000
CMD8: SEND_EXT_CSD, arg: 0x000001aa
cmdevt: wait for event & 0x1
cmdevt: 00000005
00000000 00000000 00000000 00000000
Booting from boot.bin...
Setting SDCard clk freq to 781 KHz
CMD0: GO_IDLE
cmdevt: wait for event & 0x1
cmdevt: 00000001
00000000 00000000 00000000 00000000
CMD8: SEND_EXT_CSD, arg: 0x000001aa
cmdevt: wait for event & 0x1
cmdevt: 00000005
00000000 00000000 00000000 00000000
SDCard boot failed.
No boot medium found
2023-06-06 10:02:03 +02:00
Andrew Dennison
51dd5277af
soc/integration: support software_debug for add_spi_flash()
2023-06-06 10:01:38 +02:00
Andrew Dennison
93bc2760fe
build/openfpgaloader: support jtag index-chain
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* allows loading a FPGA that is not the only device in a JTAG scan chain
2023-06-06 10:01:21 +02:00
Andrew Dennison
d60f5c221c
build/efinity: document SLEW 1 is fast
2023-06-06 10:00:49 +02:00
Andrew Dennison
f8a604e0fa
build/efinity: assert DRIVE_STRENGTH is valid
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With invalid drive strength Efinity 2021.2 fails with an unhelpful message:
"WARNING: Fail to generate summary report file"
Efinity 2022.2 does report DRIVE_STRENGTH is invalid
2023-06-06 10:00:27 +02:00
Andrew Dennison
8066a9e265
efinix/dbparser: support more Titanium pll_in pins
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* Veridied to fix using A11 on Ti60F255. Without this the wrong GPIO was silently used
* Seems to correctly select PLL_IN clock for these Ti60F255 pins:
** H6, B2, C5, E6, A11, C14, L11, R13, P11, R5, A2
2023-06-06 08:51:41 +02:00
Andrew Dennison
e10643bfd5
yosys: add command line arg to be quiet
2023-06-06 08:51:22 +02:00
Andrew Dennison
4eed62143c
litex_client: remove duplicate read
2023-06-06 08:49:54 +02:00
Andrew Dennison
5e667f17d7
csr: fix field access check
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* Broken in 5dc440e80d
2023-06-06 08:49:32 +02:00
Richard Tucker
88ec1b3f5e
tools: include LITESD in zephyr dts generator
2023-06-06 08:42:49 +02:00
Andrew Dennison
eb67197a46
tools/linux: fix dts warning: missing #address-cells
2023-06-06 08:42:35 +02:00
Andrew Dennison
9b67898e99
tools/linux: add sys_clk to device tree
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* required for using standard devm_clk_get() clock mechanism in linux drivers
2023-06-06 08:41:58 +02:00
Andrew Dennison
200a1a18ee
soc/software: move helpers to hw/common.h
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Fixes warning:
liblitespi/spiflash.c: In function 'spiflash_erase_range':
liblitespi/spiflash.c:202:4: warning: implicit declaration of function 'cdelay' [-Wimplicit-function-declaration]
cdelay(CONFIG_CLOCK_FREQUENCY/25);
^~~~~~
Fixes link failure with spiflash and without liblitedram after commit: 118dd6ed08
ld: ../liblitespi/liblitespi.a(spiflash.o): in function `spiflash_erase_range':
../liblitespi/spiflash.c:209: undefined reference to `cdelay'
2023-06-06 08:41:35 +02:00