0976c5aa54
Refactor code
2023-04-20 19:00:26 +08:00
4731aa6522
Add missing ifdef check
2023-04-20 18:46:50 +08:00
89396c7586
Add SDRAM_PHY_CLAM_SHELL guard
2023-04-20 18:45:12 +08:00
11dc5b049b
Working clam shell topology
2023-04-20 18:35:56 +08:00
b367c27191
integration/soc/zynq: Revert previous commit (incorrect), re-enable CSR decode on Zynq7000/MP and add check/error when SoCBusHandler has more than one Region and one of them has its decoder disabled.
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This will prevent silent errors and means offset needs to be added in Software.
2023-04-12 19:54:01 +02:00
f44ff2bac4
integration/soc/SoCBusHandler: Force interconnect to Crossbar when at least one region has the decoder disabled.
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See https://github.com/enjoy-digital/litex/issues/1665 since optimizations on Shared Interconnect can't be used with
disabled decoder.
2023-04-12 19:13:14 +02:00
cb9f01be9e
Merge pull request #1671 from hansfbaier/master
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give human readable error messages if a connector or pin is not available
2023-04-11 16:34:46 +02:00
748899aa49
Merge pull request #1670 from dasdgw/i2c_fix
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soc/software: fix i2c_write
2023-04-11 16:34:18 +02:00
750f8c41b9
distinguish between dict and list connectors in error message
2023-04-11 14:11:48 +07:00
cfaba189c4
give human readable error messages if a connector or pin is not available
2023-04-11 11:09:10 +07:00
b1e02ebcfa
soc/software: fix i2c_write
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commit 3fa3080e introduced an additional address length paramater to
i2c_write to support non 8bit memory addresses.
But the parameter wasn't added to the call of i2c_write in i2c_send_init_cmds.
This commit fixes the issue by adding the address length parameter to
the call of i2c_write.
2023-04-10 12:47:15 +02:00
c9e2de21f7
integration/soc: Switch from setattr to add_module.
2023-04-07 09:40:53 +02:00
dc4b748752
integration/soc/add_pcie: Add US(P) specific MSI connection.
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Will preferably have to be understood/fixed directly in the verilog adaptation.
2023-04-06 18:25:00 +02:00
0c326f0ed0
cpu/neorv32: Use older commit.
2023-03-30 12:38:27 +02:00
d299957118
cpu/neorv32: Use specific sha1, litex_core_complex will need an update.
2023-03-30 12:06:48 +02:00
ab8d906827
CHANGES.md: Update.
2023-03-30 10:13:56 +02:00
181d414911
integration/soc/add_pcie: Expose more DMA parameters.
2023-03-27 17:43:03 +02:00
4b72dd047e
Merge pull request #1662 from enjoy-digital/multi-channel-pwm
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soc/cores/pwm: Add MultiChannelPWM core reusing PWM module.
2023-03-24 18:11:55 +01:00
ffded272d4
Merge pull request #1655 from timkpaine/tkp/distfix
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Small packaging and CI changes
2023-03-24 18:08:55 +01:00
4dabf0a330
cpu/vexriscv/naxriscv: Use reserved_interrupts to reserved interrupt 0.
2023-03-24 09:02:49 +01:00
2d24f50844
soc/add_cpu: Make sure to reserve CPU's reserved interrupt when adding CPU.
2023-03-24 09:02:22 +01:00
e55f0da7c7
software/liblitesdcard: Only use sdcard_stop_transmission when nblocks > 1 (thanks @bayi).
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Similar to what is already done for reads.
2023-03-24 08:39:50 +01:00
c3e93620ec
cpu/rocket: rework variant naming convention
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The naming convention for LiteX Rocket variants has become overly
complex. Simplify it while at the same time adding more flexibility.
There is a new set of instances of varying main RAM memory bus port
width (1x (64bit), 2x (128bit), 4x (256bit), and 8x (512bit)), of
each of the following principal LiteX specific Rocket models:
- small: (rv64imac, no MMU, no S, no FPU)
- medium: (rv64imac, adds MMU and S-mode)
- linux: (rv64imafdc, adds FPU, supports linux distros)
- full: (rv64imafdcbkph[+], adds hypervisor support)
NOTE: before adding H support, the feature set of the old `full`
model is now represented by the `linux` model. The old `linux`
did not use to have an FPU, and is now available as `medium`.
In addition to the range of memory port widths, each model
will be instantiated in 1, 2, 4, and 8 core variants. The
naming convention is `LitexConfig_<model>_<num_cores>_<mem_width>`.
E.g. `LitexConfig_full_8_2` for an 8-core full model with
a 128bit main RAM AXI port. On the build command line, this
example would look like:
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--cpu-type rocket --cpu-variant full \
--cpu-num-cores 8 --cpu-mem-width 2 \
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There are a total of 4 * 4 * 4 = 64 (sub-)variants: each of the four
principal models can be fitted with one of four core counts, and one
of four memory bus widths.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2023-03-22 12:26:03 -04:00
5e5b929ee6
soc/cores/pwm: Add MultiChannelPWM core reusing PWM module.
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Also do minor changes to PWM module to allow reuse.
2023-03-22 14:52:38 +01:00
1c43a71970
Merge pull request #1636 from gatecat/cva6_rv32
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CVA6: Adding RV32 support
2023-03-22 12:06:52 +01:00
6274b0e9bf
Merge branch 'master' into cva6_rv32
2023-03-22 09:30:03 +01:00
6b362969e8
Merge pull request #1654 from shenki/rocket-cva6-csr
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cpu: rocket, cva6: Fix compilation with newer binutils
2023-03-22 09:27:49 +01:00
71b522e5db
cpu: rocket, cva6: Fix compilation with newer binutils
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Resolves the error:
cpu/rocket/irq.h:23: Error: unrecognized opcode `csrr a4,mstatus',
extension `zicsr' required
Rocket and cva6 missed this in commit 0e2a1b54a4
2023-03-22 17:41:46 +10:30
edbe8294b8
Simplify MANIFEST.in, include files relevant for distribution, add long
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description to setup.py, fix classifier tag, tweak CI to start
standardizing workflow
2023-03-21 13:28:32 -04:00
cd933da3ac
Merge pull request #1651 from trabucayre/gowinpll_complete_support
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soc/cores/clock/gowin_gw1n: add support for CLKOUTP, CLKOUTD, CLKOUTD3, phase and divisor
2023-03-20 19:41:12 +01:00
5f1a6026c8
soc/cores/clock/gowin_gw1n: add support for CLKOUTP, CLKOUTD, CLKOUTD3, phase and divisor
2023-03-20 08:00:03 +01:00
6ee39b4712
cores/cpu/vexriscv_smp/naxrisv: Fix/Shift IRQ numbering since 0 is reserved.
2023-03-17 21:33:37 +01:00
5f58753afe
Merge pull request #1650 from trabucayre/update_gowin_pll
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soc/cores/clock/gowin_gw1n: improve VCO configuration
2023-03-17 18:25:49 +01:00
94dfa81d65
soc/cores/clock/gowin_gw1n: improve VCO configuration
2023-03-17 11:12:35 +01:00
e50b5d0d45
cva6: Fix reset integration
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Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-15 16:14:19 +01:00
cbf4db076e
Merge pull request #1648 from dalegaard/bugfix/litex_term_connect_timeout
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litex_term: improve connection setup
2023-03-15 09:14:55 +01:00
3ae3d66c80
cva6_wrapper: Fix reset logic
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Without this, reset was never being asserted which caused problems on
hardware (probably because the CPU started running while the rest of the
SoC had reset asserted...)
Signed-off-by: gatecat <gatecat@ds0.me>
2023-03-14 13:03:20 +01:00
d6db2be6b6
software/liblitedram: Halve seed_array (Calibration was too long on US(+) devices) and fix write latency calibration presentation when SDRAM_DELAY_PER_DQ is not set.
2023-03-14 12:09:10 +01:00
fe714f8fe7
litex_term: improve connection setup
2023-03-14 10:48:19 +01:00
38282effd4
soc/cores/bitbang: Cosmetic cleanups.
2023-03-14 09:51:56 +01:00
c2c8504bec
soc/cores/bitbang: Revert 1256ca3767.
2023-03-14 09:42:51 +01:00
341850939e
Merge pull request #1643 from jeremyherbert/bitbang-docs
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add docstrings to bitbang
2023-03-14 09:36:38 +01:00
1256ca3767
small doc fixes, add type hints and PEP8 whitespace
2023-03-14 12:04:06 +10:00
9e08d96cb2
Merge pull request #1647 from te-johan/efinix_spi_mode
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build/efinix: add option use active or passive spi mode.
2023-03-13 21:17:02 +01:00
c2ea83db38
Merge pull request #1646 from Icenowy/gw2ar
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soc/cores/clock/gowin_gw2a: enable GW2AR support
2023-03-13 21:12:00 +01:00
60557b9e27
build/efinix: add option use active or passive spi mode.
2023-03-13 15:53:57 +01:00
b05c306908
soc/cores/clock/gowin_gw2a: enable GW2AR support
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Gowin GW2AR is just GW2A with co-packaged external RAM.
Enable using GW2APLL for GW2AR.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2023-03-13 16:46:31 +08:00
c64c89c652
add docstrings to bitbang
2023-03-11 13:41:10 +10:00
67e8d77421
tools/litex_sim: Update Video Framebuffer.
2023-03-10 13:33:55 +01:00
7bd98cf5d9
tools/litex_json2dts_linux: Fix intc0 regression.
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Introduced when disabling lintc0 generation on Rocket.
2023-03-10 09:34:00 +01:00
Jiajie Chen
Florent Kermarrec
Hans Baier
dasdgw
Gabriel Somlo
Joel Stanley
Tim Paine
Gwenhael Goavec-Merou
gatecat
Lasse Dalegaard
Jeremy Herbert
Johan Carlsson
Icenowy Zheng