Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
5,933 Commits 42 Branches 14 Tags 30 MiB
Commit Graph

5933 Commits

Author SHA1 Message Date
Jędrzej Boczar a9d8b81385 test/axi: move all AXI Lite tests to separate file 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 367eb12240 soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 8ae501c391 test/axi: add crossbar stress tests 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 706bc25dc1 soc/integration: add bus standard parser arguments 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 32d9e212c5 soc/interconnect/axi: improve Timeout module and test it with shared interconnect 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 2cab7fbf0f test/axi: add shared AXI Lite interconnect tests 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 3a08b21d44 soc/interconnect/axi: implement AXI Lite decoder 2020-07-22 17:16:33 +02:00
Jędrzej Boczar 214cfdcaeb soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to 2020-07-22 17:16:33 +02:00
Jędrzej Boczar baf23c9c9b test/test_axi: add AXI Lite interconnect arbiter tests 2020-07-22 17:16:29 +02:00
Jędrzej Boczar a8a583d6b4 socinterconnect/axi: interconnect shared sketch 2020-07-22 17:16:26 +02:00
Jędrzej Boczar f47ccdae99 soc/interconnect/axi: point-to-point interconnect and timeout module with tests 2020-07-22 17:16:12 +02:00
Jędrzej Boczar b4c1120e3d soc/integration: choose interconnect based on bus standard 2020-07-22 17:16:07 +02:00
Jędrzej Boczar 69d8dd788d soc/integration: add axi-lite standard to SoCBusHandler 2020-07-22 17:13:28 +02:00
enjoy-digital 2361abb12d
Merge pull request #599 from antmicro/gen-mmcm-pr 
litex-gen: add mmcm core
 2020-07-22 14:52:26 +02:00
Piotr Binkowski 66c5f37133 litex-gen: add mmcm core 2020-07-22 12:34:32 +02:00
Florent Kermarrec 6b72f52c5d boards: keep in sync with litex-boards. 2020-07-22 08:50:38 +02:00
Florent Kermarrec 1f27b7405e soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. 2020-07-21 19:54:42 +02:00
Florent Kermarrec 408d1a9f5d cpu/vexriscv/system.h: update flush_cpu_dcache. 2020-07-21 19:43:00 +02:00
Florent Kermarrec 47ce15b431 interconnect/wishbone: add minimal UpConverter. 2020-07-21 19:35:14 +02:00
enjoy-digital 9fc488bdf6
Merge pull request #597 from antmicro/jboc/litex-buildenv-add-adapter-fix 
Fix Vivado crash when using 1:1 wishbone.Converter
 2020-07-20 23:11:01 +02:00
enjoy-digital b92519502a
Merge pull request #595 from betrusted-io/master 
wire up missing register bits.
 2020-07-20 22:47:16 +02:00
enjoy-digital 87d7f6e72e
Merge pull request #598 from sergachev/master 
interconnect/csr_bus: fix paged access warning
 2020-07-20 19:24:21 +02:00
Ilia Sergachev 8656ea9b67 interconnect/csr_bus: fix paged access warning 2020-07-20 18:23:09 +02:00
Jędrzej Boczar 07bc589c41 fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed 
Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
cc003bef3a
and litex bumped to 4a18b828bc,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
 2020-07-20 15:26:21 +02:00
Florent Kermarrec 4a18b828bc software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz. 2020-07-20 13:48:49 +02:00
Florent Kermarrec 100aa5a4ca soc/cores/spi/SPIMaster: rewrite/simplify. 
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
 2020-07-20 10:44:18 +02:00
bunnie 53a567daef wire up missing register bits. 
Not sure how they went missing...but just noticed them.
 2020-07-19 03:00:25 +08:00
Florent Kermarrec 63c19ff45f liblitesdcard/spisdcard: update comments. 2020-07-17 15:39:39 +02:00
Florent Kermarrec 1f34f6ef00 soc/cores/spi: make sure done and miso are synchronous. 2020-07-17 15:38:52 +02:00
Florent Kermarrec 754f140a9d spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now. 2020-07-17 11:58:26 +02:00
Florent Kermarrec 8143f1a08b soc/cores/spi: make sure miso is stable during xfer. 2020-07-17 11:56:27 +02:00
Florent Kermarrec ac35e158c1 bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr. 
For example:
{
	"Image":  "0x40000000",
	"bootargs": {
		"r1":  "0x12345678",
	}
}

will copy Image to 0x40000000 and set r1 to 0x12345678.

By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
}

is equivalent to:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
	"bootargs": {
		"r1":   "0x00000000",
		"r2":   "0x00000000",
		"r3":   "0x00000000",
		"addr": "0x00000000",
	}
}
 2020-07-16 18:12:11 +02:00
enjoy-digital ee4b1d81a7
Merge pull request #594 from antmicro/jboc/axi-lite 
Add AXILiteDownConverter
 2020-07-16 17:56:33 +02:00
Jędrzej Boczar 229da572ff soc/interconnect/axi: propagate response errors in AXILiteDownConverter 2020-07-16 17:16:35 +02:00
Jędrzej Boczar 93bcc94b53 soc/interconnect/axi: implement AXILite down-converter 2020-07-16 17:02:49 +02:00
enjoy-digital 21c48eed76
Merge pull request #593 from antmicro/jboc/axi-lite 
Add AXILite components: AXILiteSRAM and AXILite2CSR
 2020-07-16 11:56:57 +02:00
Jędrzej Boczar 0be607dad9 soc/integration: revert `bus` argument for add_ram/add_rom 2020-07-16 10:26:12 +02:00
Jędrzej Boczar 2700ec3ce5 soc/integration: use AXILiteConverter (dummy implementation) in add_adapter() 2020-07-15 15:59:16 +02:00
Jędrzej Boczar f3072d4984 soc/interconnect/axi: add connect methods for convenience 2020-07-15 15:48:40 +02:00
Jędrzej Boczar 78a631f392 test/axi: add AXILite2CSR and AXILiteSRAM tests 2020-07-15 12:40:39 +02:00
enjoy-digital e12bebb8e1
Merge pull request #592 from antmicro/fix-symbiflow-makefile 
symbiflow: changed toolchain command names in Makefile
 2020-07-15 12:08:21 +02:00
Jędrzej Boczar a5be2cd257 soc/interconnect/axi: improve SRAM/CSR access speed 2020-07-15 11:44:14 +02:00
Alessandro Comodi 3f7568de09 symbiflow: changed toolchain command names in Makefile 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-07-15 11:31:06 +02:00
Jędrzej Boczar d8a242d86f soc/interconnect: add AXILite SRAM 2020-07-15 10:58:34 +02:00
Jędrzej Boczar b692b2a3f1 soc/interconnect: add AXILite2CSR bridge 2020-07-15 10:36:34 +02:00
Jędrzej Boczar 35149c4e80 soc/integration: update add_adapter to convert between AXILite/Wishbone 2020-07-14 16:31:46 +02:00
Florent Kermarrec 6671eb6218 build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. 
Using fast-read as default prevent loading the .bit via JTAG (see #589).
 2020-07-13 11:55:03 +02:00
Florent Kermarrec ae3c78f6d1 build/lattice/trellis: fix spimode typo. 2020-07-11 21:30:19 +02:00
enjoy-digital 7c381dadc2
Merge pull request #588 from oskirby/trellis-spimode 
trellis: Add option to select SPI mode.
 2020-07-11 21:26:55 +02:00
Owen Kirby 0aec5b0f8c trellis: Add option to select SPI mode. 
This allows a significant speedup when booting large bitstreams on ECP5
boards that support dual or quad SPI operation.
 2020-07-11 11:48:10 -07:00