Sebastien Bourdeauducq
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0e00837f42
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asmicon: move slot time to timing settings
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2012-03-18 14:57:31 +01:00 |
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Sebastien Bourdeauducq
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b1eb919ad2
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asmicon: bank machine (untested)
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2012-03-18 00:12:03 +01:00 |
|
Sebastien Bourdeauducq
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5f28103769
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corelogic/fsm: delayed enters
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2012-03-18 00:09:40 +01:00 |
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Sebastien Bourdeauducq
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a4294762d0
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corelogic/roundrobin: CE switching
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2012-03-16 16:54:47 +01:00 |
|
Sebastien Bourdeauducq
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7c377880fa
|
asmicon: refresher (untested)
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2012-03-15 20:29:26 +01:00 |
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Sebastien Bourdeauducq
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e3ef121440
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norflash: use new timeline API
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2012-03-15 20:26:04 +01:00 |
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Sebastien Bourdeauducq
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e969b9afc3
|
corelogic: convert timeline to function and move to misc
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2012-03-15 20:25:44 +01:00 |
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Sebastien Bourdeauducq
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7b14e0bd05
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asmicon: skeleton
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2012-03-14 18:26:05 +01:00 |
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Sebastien Bourdeauducq
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1665f293a6
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bus/asmibus/hub: require finalization before get_slots
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2012-03-14 16:19:29 +01:00 |
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Sebastien Bourdeauducq
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5c0cc6292c
|
fhdl: export log2_int
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2012-03-14 12:19:42 +01:00 |
Alain Péteut
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97fece249d
|
setup.py: simplify
Signed-off-by: Alain Péteut <alain.peteut@yahoo.com>
|
2012-03-11 00:52:13 +01:00 |
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Sebastien Bourdeauducq
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f6e76ae198
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doc: more examples and comments
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2012-03-10 19:38:39 +01:00 |
|
Sebastien Bourdeauducq
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1f4c58ee26
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doc: cosmetic changes (thanks sh4rm4 for reporting typos)
|
2012-03-10 17:59:42 +01:00 |
|
Sebastien Bourdeauducq
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78c707e354
|
doc: use script font
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2012-03-09 21:57:50 +01:00 |
|
Sebastien Bourdeauducq
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7b1101ab99
|
doc: simulation
|
2012-03-09 21:17:21 +01:00 |
|
Sebastien Bourdeauducq
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0165d23295
|
doc: cosmetic changes (thanks rofl0r for reporting typos)
|
2012-03-09 18:26:00 +01:00 |
|
Sebastien Bourdeauducq
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59db4e9106
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doc: add logo
|
2012-03-09 17:16:33 +01:00 |
|
Sebastien Bourdeauducq
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90546fd811
|
doc: switch to sphinx
|
2012-03-09 17:08:38 +01:00 |
|
Sebastien Bourdeauducq
|
57a87b3316
|
examples: FIR filter simulation
|
2012-03-08 20:49:36 +01:00 |
|
Sebastien Bourdeauducq
|
bfcd4e636b
|
fhdl: handle negative constants correctly
|
2012-03-08 20:49:24 +01:00 |
|
Sebastien Bourdeauducq
|
f4adb0fe9c
|
examples: remove outdated wb_intercon simulation
|
2012-03-08 18:17:56 +01:00 |
|
Sebastien Bourdeauducq
|
84aa703447
|
vpi: support extra include directories
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2012-03-08 18:14:40 +01:00 |
|
Sebastien Bourdeauducq
|
bbaadebf68
|
gitignore: update
|
2012-03-08 18:14:19 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
|
2012-03-08 18:14:06 +01:00 |
|
Sebastien Bourdeauducq
|
ddc0e49981
|
vpi: patch for Icarus Verilog
|
2012-03-08 17:27:59 +01:00 |
|
Sebastien Bourdeauducq
|
59a57e7a76
|
examples: small cleanup
|
2012-03-08 15:55:02 +01:00 |
|
Sebastien Bourdeauducq
|
678a89d572
|
sim: fix zero encoding
|
2012-03-08 15:34:08 +01:00 |
|
Sebastien Bourdeauducq
|
decbd069fa
|
sim: fix message debug formatting
|
2012-03-08 15:27:35 +01:00 |
|
Sebastien Bourdeauducq
|
98e96b3952
|
sim: make initialization cycle optional (selectable by function attribute)
|
2012-03-06 19:43:59 +01:00 |
|
Sebastien Bourdeauducq
|
8160ced2e9
|
sim: memory access
|
2012-03-06 19:29:39 +01:00 |
|
Sebastien Bourdeauducq
|
db8f8bf2e3
|
fhdl: register memory objects with namespace
|
2012-03-06 18:33:44 +01:00 |
|
Sebastien Bourdeauducq
|
6f829c7afc
|
sim: support for signed numbers
|
2012-03-06 16:46:18 +01:00 |
|
Sebastien Bourdeauducq
|
90184b22d2
|
fhdl/verilog: fix signed constant conversion
|
2012-03-06 16:45:44 +01:00 |
|
Sebastien Bourdeauducq
|
0a23cadd38
|
vpi: install target
|
2012-03-06 15:51:09 +01:00 |
|
Sebastien Bourdeauducq
|
9da512dbf5
|
sim: VCD generation
|
2012-03-06 15:26:04 +01:00 |
|
Sebastien Bourdeauducq
|
22b3c11b93
|
sim: clean startup/shutdown
|
2012-03-06 15:00:02 +01:00 |
|
Sebastien Bourdeauducq
|
06de17b16c
|
sim: remove temporary files and socket
|
2012-03-06 14:20:26 +01:00 |
|
Sebastien Bourdeauducq
|
7230508e7c
|
fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
|
2012-03-06 14:18:22 +01:00 |
|
Sebastien Bourdeauducq
|
2c375e900f
|
sim: remove default sockaddr
|
2012-03-06 13:58:49 +01:00 |
|
Sebastien Bourdeauducq
|
8d16fde48c
|
fhdl: add simulation functions in fragment
|
2012-03-06 13:58:22 +01:00 |
|
Sebastien Bourdeauducq
|
aac9752558
|
sim: basic functionality working
|
2012-03-05 20:31:41 +01:00 |
|
Sebastien Bourdeauducq
|
c4c22c9ca0
|
sim: signal writes working
|
2012-03-05 15:40:21 +01:00 |
|
Sebastien Bourdeauducq
|
9bbec278c6
|
sim: cleanups
|
2012-03-04 22:56:56 +01:00 |
|
Sebastien Bourdeauducq
|
2cd71e4b5e
|
sim: signal reads working
|
2012-03-04 22:33:03 +01:00 |
|
Sebastien Bourdeauducq
|
c0b0161ec9
|
sim: compile VPI module
|
2012-03-04 21:27:02 +01:00 |
|
Sebastien Bourdeauducq
|
29859acc34
|
sim: two way IPC working
|
2012-03-04 19:17:03 +01:00 |
|
Sebastien Bourdeauducq
|
8586daf2dd
|
sim: IPC module (lacks str/int encoding)
|
2012-03-03 18:55:38 +01:00 |
|
Sebastien Bourdeauducq
|
7f307c54a9
|
README: clarify license
|
2012-02-29 20:30:08 +01:00 |
|
Sebastien Bourdeauducq
|
8d4a42887e
|
ddrphy: working on hardware, simulation a bit messed up
|
2012-02-24 15:44:51 +01:00 |
|
Sebastien Bourdeauducq
|
baba267db6
|
ddrphy: request wrdata_en/rddata_en at the same time as the command
|
2012-02-24 15:14:58 +01:00 |