b014c7194b
build/lattice/trellis: also generate bitstream in svf format
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Before being able to program the board (e.g., with openocd), one
would have to convert the bitstream file to .svf using a python
script included with the source trellis distribution. However,the
trellis 'ecppack' utility can also generate .svf bitstream files
directly.
2019-03-06 16:29:18 -05:00
317dba8314
software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation
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In the future, the PHYs should generated these constants.
2019-03-05 18:03:24 +01:00
7de1fe519a
targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC
2019-03-05 13:27:11 +01:00
ca63db4040
bios/sdram: use burstdet detection for ECP5DDRPHY init
2019-03-05 13:27:06 +01:00
2ebfab5e1f
Merge pull request #150 from daveshah1/trellis_bus_fixes
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lattice/common: Fix tristate buses with Trellis
2019-03-04 12:00:44 +01:00
ebe8f600e1
lattice/common: Fix tristate buses with Trellis
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Signed-off-by: David Shah <dave@ds0.me>
2019-03-04 10:50:56 +00:00
935f3a5337
boards/ulx3s: add device selection parameter
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ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F
2019-03-04 09:40:14 +01:00
e6f97e08d2
targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25
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Now supported by Trellis/Nextpnr.
2019-03-04 09:27:31 +01:00
5ef28bdf75
build/lattice/trellis: add package support
2019-03-01 15:20:02 +01:00
1b34c07da9
build/lattice/trellis: basecfg now integrated in nextpnr
2019-03-01 14:20:00 +01:00
7e995eb418
boards/targets/ulx3s: allow building with diamond or trellis
2019-03-01 13:59:28 +01:00
4bf789eab9
soc/software/bios/boot: add vexriscv workaround
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Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
2019-03-01 09:16:48 +01:00
1fd81c2882
soc/integration: add initial SoCZynq SoC
2019-02-27 22:39:35 +01:00
3c527dcbdf
soc/interconnect: add initial axi code with bus definition and AXI2Wishbone
2019-02-27 22:26:57 +01:00
ed2578799b
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
2019-02-27 22:24:56 +01:00
4aa07f2ae9
soc/interconnect: rename axi to axi_lite
2019-02-27 22:11:09 +01:00
6a4c133cd2
test: add basic test_csr
2019-02-27 21:46:00 +01:00
c9f9e237d9
Merge pull request #149 from daveshah1/versa_trellis
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Add trellis build option to versa_ecp5 and bring trellis support up to date
2019-02-25 19:26:07 +01:00
ff7e0fab6a
versa_ecp5: Add option to build with Trellis
2019-02-25 18:02:04 +00:00
024b41c5b2
trellis: Add LPF frequency constraints and remove -nomux
2019-02-25 18:01:35 +00:00
e38dfd99e8
soc/software/sdram: fix compilation on ultrascale
2019-02-25 16:12:21 +01:00
5f29a12ee7
targets/versa_ecp5: integrate DDR3
2019-02-25 15:27:08 +01:00
3dd529e40b
soc/software/bios/sdram: add ECP5 support
2019-02-25 14:41:33 +01:00
2fd6d0e7e1
soc/software/bios/sdram: improve write_level robustness
2019-02-25 14:38:24 +01:00
36772b75f6
soc/software/bios/sdram: improve sdrlevel readibility
2019-02-25 14:37:31 +01:00
6a980781d3
soc/software/bios/sdram: add helpers for rst/inc of delays
2019-02-25 14:36:47 +01:00
dad7b292aa
Merge pull request #148 from daveshah1/versa_remove_n
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versa_ecp5: Remove negative diff IO pins
2019-02-22 14:32:45 +01:00
321dd8fcf6
versa_ecp5: Remove negative diff IO pins
...
In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)
These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').
Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.
2019-02-22 12:12:10 +00:00
c03b1ad13a
platforms/versa_ecp5: add ddram pins
2019-02-20 22:45:19 +01:00
ff155a474d
soc/tools/remote/comm_uart: be sure to flush in waiting bytes before read and write
2019-02-16 00:08:24 +01:00
d3ecdd9995
soc/cores/clock: add actual clk_freqs to config
2019-02-14 10:41:27 +01:00
af52842fbb
soc_sdram: add use_full_memory_we parameter to allow disabling vivado workaround on small l2 caches
2019-02-12 12:12:40 +01:00
32543430c0
build/lattice/common/LatticeECXTrellisImpl: add support for nbits == 1
2019-02-11 19:41:12 +01:00
aabf042d38
soc_sdram: don't generate sdram initialization error message when integrated_main_ram is used
2019-02-11 09:23:39 +01:00
f51ad43607
build/lattice/common: add LatticeiCE40DDROutput
2019-02-07 16:23:55 +01:00
22ccf9ddf1
platforms/nexys_video: add LPC transceivers pins
2019-02-01 23:39:17 +01:00
1d9c55888f
build/sim: add jtagremote module (thanks LamdaConcept)
2019-01-30 14:01:19 +01:00
57b8bdd530
soc/integration/soc_core: allow disabling wishbone timeout
2019-01-29 12:47:11 +01:00
05dcb5cadc
soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
2019-01-27 08:28:01 +01:00
02708d3b0f
boards/platform/kc705: add sfp pins (both tx and rx)
2019-01-23 08:40:47 +01:00
8344a6a4ef
soc/cores/clock: add USIDELAYCTRL
2019-01-22 12:50:05 +01:00
7e0dd37616
soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when it's not the case
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With ECC configurations, native port data_width is not necessarily a power of 2.
2019-01-22 09:08:35 +01:00
871b958f85
boards/targets: improve presentation
2019-01-21 10:40:41 +01:00
a318343afb
boards/platforms/kcu105: add si570_refclk
2019-01-21 10:40:37 +01:00
48312890e5
boards/platforms/kc705: use vivado as default programmer
2019-01-21 10:40:32 +01:00
1b23890e0d
soc/cores/clock: allow ClockSignal to be used for clkin
2019-01-16 22:05:52 +01:00
387ee04130
build/sim/core: fix coverage
2019-01-11 15:01:58 +01:00
482abf9b43
build/sim/core: set -Wno-BLKANDNBLK (prevent blocking/non-blocking assigns on a same structure in system verilog)
2019-01-11 13:51:15 +01:00
9c5f654773
build/sim/core: set unroll-count to 256 to prevent Error-BLKLOOPINIT
2019-01-11 13:39:09 +01:00
f132012de1
build/sim: disable Warning-WIDTH
2019-01-10 16:03:09 +01:00
Gabriel L. Somlo
Florent Kermarrec
David Shah
David Shah