d13ac3b3d5
cpu/mor1kx: Adding verilog include directory.
2018-10-03 21:57:24 -07:00
9a44f08a3e
build/platforms: Add ice40_hx8k_b_evn from Migen.
2018-10-03 20:53:33 -04:00
dc7cd75757
build.xilinx: Run `phys_opt_design` and generate timing report.
...
Makes the flow more similar to migen.
2018-10-03 16:02:43 -07:00
948527b0fe
cores/cpu: revert vexriscv (it seems there is a regression in last version)
2018-10-02 12:30:11 +02:00
15bca4535f
targets/sim: fix integrated_main_ram_size when with_sdram
2018-10-02 11:31:08 +02:00
6e327cda26
bios/sdram: rewrite write_leveling (simplify and improve robustness)
2018-10-01 15:38:19 +02:00
975be6686f
platforms/genesys2: add eth clock timing constraint
2018-10-01 15:37:34 +02:00
934a5da559
soc/cores/clock: add expose_drp on S7PLL/S7MMCM
2018-09-28 13:02:10 +02:00
9097573e71
Merge pull request #109 from cr1901/xip-improve
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Improve XIP Support
2018-09-25 15:32:04 +02:00
082b03016c
targets: use new clock abstraction on all 7-series targets
2018-09-25 09:31:30 +02:00
74e74dc0e7
soc/cores/clock: different clkin_freq_range for pll and mmcm
2018-09-25 09:09:47 +02:00
91d8cc2d6a
soc/cores/clock: different vco_freq_range for pll and mmcm
2018-09-25 09:04:38 +02:00
6cd954940c
soc/core/clock: allow selecting buffer type (None, BUFG, BUFR). (default = BUFG)
2018-09-25 08:36:18 +02:00
912ca3236b
soc/cores/clock: create specific S7IDELAYCTRL module
2018-09-24 23:22:59 +02:00
baec87f530
soc/cores/clock: add S7MMCM support
2018-09-24 23:20:12 +02:00
ef40524924
soc/cores/clocks/S7PLL: add speedgrade support, default to -1 (slowest)
2018-09-24 22:58:23 +02:00
5415b521be
targets/arty: use new clock abstraction module (compile, untested on board)
2018-09-24 22:49:30 +02:00
63fc395006
soc/cores: init clock abstraction module
2018-09-24 22:49:01 +02:00
0ff6d58605
Distinguish crt0 variants more clearly, update BIOS to use CTR variant (as it has no .data section).
2018-09-24 14:48:54 -04:00
8106008184
integration/builder: Create EXECUTE_IN_PLACE Makefile variable to complement COPY_TO_MAIN_RAM.
2018-09-24 12:28:45 -04:00
db90619067
integration/builder: Add LiteX define to generated variables (to distinguish MiSoC and LiteX).
2018-09-24 11:04:57 -04:00
70a32ed86f
sim/verilator: add multithread support (default=1)
2018-09-24 12:43:29 +02:00
7f0d116d88
soc_core: use cpu instead of cpu_or_bridge internally (keep retro-compat for now)
2018-09-24 10:59:32 +02:00
22febe9582
boards/targets: uniformize things between targets
2018-09-24 10:58:10 +02:00
01b025aafd
soc_core/get_mem_data: add endianness support and use it in builder/initialize_rom to avoid duplication
2018-09-24 08:01:32 +02:00
b528a005a0
cores/cpu: add software informations to cpu and simplify cpu_interface
2018-09-24 07:51:41 +02:00
2d785cb0ac
boards/plarforms: fix issues found while testing simple design on all platforms
2018-09-24 02:03:30 +02:00
0b0e3ac1dd
test/test_targets: test simple design with all platforms
2018-09-24 02:02:14 +02:00
c88029d330
soc_core: add uart-stub argument
2018-09-24 02:01:15 +02:00
0d2d3959f1
setup.py: add litex_simple exec (to ease building simple design)
2018-09-24 01:24:51 +02:00
e04530e0c4
test/test_targets: update and reorganize targets
2018-09-24 01:15:33 +02:00
e9ed737037
ease RemoteClient import
2018-09-23 10:23:00 +02:00
346dcf94dc
Merge pull request #108 from xobs/use-csr-accessors
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Use csr accessors when generating `csr.h`
2018-09-23 09:59:37 +02:00
6f25a0d8a1
csr: use external csr_readl()/csr_writel() if present
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If the variable CSR_ACCESSORS_DEFINED is set, then use external
csr_readl() and csr_writel() instead of locally-generated inline
functions.
With this patch, csr.h can be used with etherbone.h and litex_server to
prototype drivers remotely.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:55:09 +02:00
9a252e367c
csr: use readl()/writel() accessors for accessing mmio
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Instead of directly dereferencing pointers, use variants on readl()/writel().
This way we can replace these functions with others for remote access
when writing drivers and code outside of the litex environment.
Signed-off-by: Sean Cross <sean@xobs.io>
2018-09-22 16:54:46 +02:00
1c1d87f845
Merge pull request #106 from cr1901/data-crt0
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libbase/crt0-lm32.S: Add provisions for loading .data from flash.
2018-09-22 15:21:35 +01:00
9d4da737ff
libbase/crt0-lm32.S: Add provisions for loading .data from flash.
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:100644 100644 e0cd7153
2018-09-21 10:23:14 -04:00
01ae7d4235
README: add migen/litex clarification
2018-09-21 07:37:31 +02:00
15e584d880
targets/sim: generate analyzer.csv
2018-09-20 12:20:48 +02:00
cde72603a1
targets/sim: generate csr.csv
2018-09-20 11:17:18 +02:00
f62df5023f
targets/sim: add rom-init
2018-09-20 01:14:00 +02:00
1dbf591e78
targets/sim: add ram-init param to allow initializing ram from file (faster than tftp)
2018-09-20 01:00:13 +02:00
9893c2460a
integration/soc_core: add get_mem_data function to read memory content from file
2018-09-20 00:46:06 +02:00
a3eb2e403b
soc/intergration/builder: fix when no sdram
2018-09-19 23:59:42 +02:00
934b08ede8
targets/sim: merge in a single class and ease configuration
2018-09-19 23:59:15 +02:00
bd42b18856
Merge branch 'master' of http://github.com/enjoy-digital/litex
2018-09-19 19:21:14 +02:00
3e77ae788f
targets: replace MiniSoC with EthernetSoC
2018-09-19 19:19:50 +02:00
badd992469
targets/sim: add EtherboneSoC target (allow accessing wishbone over in simulation with litex_server)
2018-09-19 19:17:32 +02:00
537b0e9058
Merge pull request #101 from cr1901/icestorm-migen-pull
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Icestorm Improvements
2018-09-18 08:19:09 +02:00
5c83c88128
Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run.
2018-09-17 21:17:24 -04:00
Tim 'mithro' Ansell
William D. Jones
Florent Kermarrec
Sean Cross